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Old 10-17-2004, 01:10 PM
Martin Schoeberl
Posts: n/a
Default Re: JOP on Spartan-3 Starter Kit

>> > > This thread turns out into a contest to build the fastest JOP
> version.
>> > > Choose an FPGA vendor of your choice and optimize HDL and tool
>> > > settings.
>> > > Maybe Martin should donate one of his boards to the winner ;-)
>> >
>> > OK, that's a good idea!
>> > Here's the contest in two categories:
>> > The smallest JOP in LC/LE count.
>> > The fastest JOP in turn of fmax.

And the WINNER of the ACEX FPGA board is: Kolja!

He changed the multiplier and suggested changes in the ALU (stack.vhd).
These two changes with a little bit of optimization by myself resulted in
a saving of 136 LCs (with default synthesizer options).
The suggestion from Paul for the Quartus settings reduced the area by another
130 LCs or 184 LCs (minimize Area). However, Koljas VHDL changes reduce
the area in the Cyclone and Spartan-3 version of JOP.

To Paul: I hope you can accept this decision. And it makes more sense to send
an ACEX board to a Xilinx user than to an Altera employee ;-)

To Kolja: Please drop me a note with your address.

The results of JOP on Cyclone and Spartan-3 (both fastest speed grade):

Cyclone, opt. for speed: 1800 LCs, fmax: 100MHz
Cyclone, opt. for area: 1746 LCs, fmax: 98MHz
Spartan-3, opt. for speed: 1844 LCs, fmax: 83MHz
Spartan-3, opt. for area: 1689 LCs, fmax: 74MHz

If you need a very small JOP core you can implement the multiplier and the
barrel shifter in software. Without the uart and the timer this results in
1077 LCs (at 98MHz) in the Cyclone.


PS.: The optimized versions of JOP are uploaded on the website.
JOP - a Java Processor core for FPGAs:

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