FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 08-27-2003, 09:48 AM
Sasa Bremec
Guest
 
Posts: n/a
Default Re: DA FIR filter vs. MAC FIR filter

Ray thanks for the answer! Searching this forum I also found your past

answers to this question.



> You are missing some key pieces of information: the available clock


frequency

> (this is different than the sample rate), and the target FPGA family.




The device is Virtex2 Pro. Its system clock is 108MHz or 125 MHz not decided

yet. And the filter coefficients are constant (not reconfigurable).



I have some additional question about FIR filter and its decimation

capability.



In my DDC after a CIC filter I would like to place this FIR filter, the

question is:



Is better to use FIR with decimation capability, or to use higher decimation

rate in CIC filter and use the FIR only as low pass filter?



CIC decimation is 32



FIR decimation is 4



The second way will allow me to do a time multiplex of this FIR because I

will have instead of 1/32 Fs the 1/128 Fs and also the number of taps will

be reduced, is this correct. Also this Fs is low enough to use MAC FIR.



Best regards, Sasa






Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Mean value filter [email protected] Verilog 15 12-22-2005 12:09 PM
FIR Filter Model priya Verilog 4 08-18-2005 11:32 PM
PolyPhase Fir filter? priya Verilog 2 06-07-2005 01:58 AM


All times are GMT +1. The time now is 06:20 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2021, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved