FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 09-22-2003, 05:34 PM
Chen Wei Tseng
Guest
 
Posts: n/a
Default Re: Configuration Options:

Rider,

When configuring the FPGA via JTAG, iMPACT will provide TCK. When
configuring the FPGA via PROM with Master Serial Setup, CCLK is provided
by the FPGA.

At the end of configuration, the FPGA will enter the startup sequence.
Treat this sequence as a state machine that the FPGA needs to go through
before "waking up". This sequence is where you can set the options of
when you want the DONE pin to go high, the IO tri-state to be released,
etc.

To get through this startup sequence, you'll need to provide clocks.
Generally, when configuring via JTAG, you would select startup clock to
be JTAGCLK since you're already providing TCK. So when configuring with
PROM, you would want to set startup clock to CCLK unless you'll be
seperating providing TCK (JTAGCLK) or even userclock to clock through
the startup sequence.

And as for PROM file generation or ACE file generation, the iMPACT help
topic has been vastly improved in 6.1i. If anything isn't clear, please
do contact the Xilinx Hotline Support.

As far as support for patform flash proms, please make sure you use 5.2i
service pack 3 for file generation.

Regards, Wei
Xilinx Applications

rider wrote:
> Hi!
> Thanks for the group to reply my previous query "Xilinx Parallel Cable
> 4 (PC4) and Platform Flash JTAG". Specially to Antti Lorenzo and
> Aurelian Lazarut. Continuing with the same topic of configuration, i
> have a few more queries:
>
> 1)In the Xilinx's latest document "Configuration Quick Start
> Guidelines" http://www.xilinx.com/bvdocs/appnotes/xapp501.pdf page 13,
> the author shows a snap from iMPACT software(fig: 9 Startup options
> for Virtex and Spartan 2). The author states:
>
> "Start-Up Clock The bitstream must be generated with the appropriate
> startup clock option for the PART to be configured properly. The
> "Start-Up Clock" option by default is set to "CCLK" for Master Serial
> Mode. When generating a bitstream for Boundary Scan (JTAG) Mode the
> option must be set to "JTAGCLK" in the pull-down menu of the GUI or
> using bitgen's command line:
> For configuring using Boundary Scan (JTAG):
> bitgen g startupclk:jtagclk designName.ncd
> For configuring via Master-Serial:
> bitgen g startupclk:cclk designName.ncd"
>
> My question is that when she talks of Master Serial Mode and CCLK,
> does she mean she is creating a file for PROM only[PART is PROM here],
> because Master Serial mode requires a PROM . The file cannot be loaded
> directly to FPGA. And when she talks of JTAG and jtagclk, the PART
> could be PROM or FPGA ? Am i right ?
>
> 2) I have Xilinx ISE5.1 , does it support the configuration of latest
> Xilinx Platform PROM XCF02S via JTAG?
>
> Thanks


Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
MI5 Persecution: Options 21/9/95 (563) [email protected] Verilog 0 06-08-2007 02:29 PM
ncverilog: command line options Prashanth Verilog 1 03-06-2006 10:55 AM
Verilog Options Bill82 Verilog 0 10-20-2004 12:54 PM


All times are GMT +1. The time now is 05:58 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved