FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal


Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 07-08-2003, 07:30 PM
Posts: n/a
Default Re: About BRAM in VirtexII

You haven't really given us enough information - you should post a little
more about the problem; are you getting an error or warning from the
simulation, and if so, what exactly is happening around the time of the
error. Also we need to know a little more about your application.

Are you using the same clock for both ports of the ram (i.e. are CLKA and
CLKB driven from the same BUFG). If so, there is one condition where reading
and writing to the same address is legal - if the port doing the write is
set to "READ_FIRST" (an attribute set on the RAM), then the data returned
from the read port is the previous contents of the RAM. You also don't
specify if the two ports of the RAM are the same widths.

That being said, you say that you have "logic to avoid hits over the same
address", meaning you are (trying to) guarantee that you never attempt a
simultaneous read and write to the same address. In the past, we have had
some problems with the simulation models of the CoreGen RAMs; we definately
had situations where the model would erroneously declare a read/write
conflict (i.e. there have been bugs in the simulation models in the past).
So, the question is, are you sure there is no conflict. It should be easy to
verify by looking at the waveforms (capuring all the inputs and outputs of
the Dual Port RAM in question). If you are getting an error, look at the
waveforms around this error to determine if you are indeed writing and
reading to the same address (or similar addresses) at the same time.
Remember, if the port wirths of the two ports are not the same, then the
"same address" from the point of view of the RAM is not simply ADDRA ==
ADDRB; if portA is 16 bits wide and portB is 4 bits wide then a contention
exists when ADDRB/4==ADDRA


"Nap" <[email protected]> wrote in message
news:[email protected] om...
> Hi guys.
> I'm working on a project using a HW platform with an XC2V300FG676-5.
> In my design I used Dual Ports BRAM produced by Coregen 4.2i (in Fndtn
> 4.2i). In simulation of the logic I faced the following problem:
> I wrote data on Port#A but when tried to read them back using port#B I
> realized that have been altered. Xilinx claims in Answer Record 10462
> that this condition
> has to do with conflict resolution over the BRAM (same Read address on
> Port#B with write address on port#A). The answer they provide does not
> help me at all because I have alot and complicated logic in order to
> avoid hits over same address. Does anybody knows if this condition
> affects only simulation?
> Thanks in advanced
> Nap

Reply With Quote


Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On

Similar Threads
Thread Thread Starter Forum Replies Last Post
Re: About BRAM in VirtexII Steve Casselman FPGA 0 07-08-2003 06:04 PM

All times are GMT +1. The time now is 07:51 PM.

Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved