I think of guard bits as extra MSBs to prevent overflow. With CORDIC,

worst case you need 2 to accommodate the gain (1.65) plus rotation of the

worst case vector on (45 degree line, full scale I and Q) to a cardinal

axis, which gives a 'gain' of sqrt(2) on one axis. CORDIC also suffers

from some truncation errors at each iteration due to the right shift of

the cross components. If you simply truncate at each iteration, the worst

case error is roughly log2(iterations) bits, which tells you the number of

bits extra you should keep in the LSBs to minimize the trucation error at

the output.

I'm not aware of a multiply-accumulate or divide-accumulate directly,

however the CORDIC can be modified to do multiplication or division and

then it is a simple matter to accumulate the results with an extra adder.

I describe the multiplication and division algorithms for CORDIC in my

CORDIC paper, which I think you have probably seen.

Jeff wrote:

> Hi,

> I have learned about CORDIC from this group, especially from Ray. Now,

> I have several more questions.

> One paper described the implement structure of CORDIC algorithm. It

> uses 16 bits data width and 6 guard bits internally. What is the guard

> bits? I have borrowed several digital design books from library and

> they do not mention that. Even though I can guess guard bits are used

> for overflow prevention, it is far away from understanding the

> utilization of its application in the CORDIC algorithm.

> My another question is how to realize an MAC(multiply-and-accumulate)

> and DAC(divide-and-accumulate) using CORDIC. The paper says they can.

> Although I have read the relevant papers on the website of Ray, I have

> not got the answer. Could you shed some light on this question?

>

> Thans in advance
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