FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 01-06-2004, 03:18 PM
Jeff
Guest
 
Posts: n/a
Default Questions about guard bits in CORDIC algorithm

Hi,
I have learned about CORDIC from this group, especially from Ray. Now,
I have several more questions.
One paper described the implement structure of CORDIC algorithm. It
uses 16 bits data width and 6 guard bits internally. What is the guard
bits? I have borrowed several digital design books from library and
they do not mention that. Even though I can guess guard bits are used
for overflow prevention, it is far away from understanding the
utilization of its application in the CORDIC algorithm.
My another question is how to realize an MAC(multiply-and-accumulate)
and DAC(divide-and-accumulate) using CORDIC. The paper says they can.
Although I have read the relevant papers on the website of Ray, I have
not got the answer. Could you shed some light on this question?


Thans in advance
Reply With Quote
  #2 (permalink)  
Old 01-06-2004, 05:24 PM
Larry Doolittle
Guest
 
Posts: n/a
Default Re: Questions about guard bits in CORDIC algorithm

In article <[email protected] >, Jeff wrote:
> I have learned about CORDIC from this group, especially from Ray.


Me, too. ;-)

> Now, I have several more questions.
> One paper described the implement structure of CORDIC algorithm. It
> uses 16 bits data width and 6 guard bits internally. What is the guard
> bits? I have borrowed several digital design books from library and
> they do not mention that. Even though I can guess guard bits are used
> for overflow prevention, it is far away from understanding the
> utilization of its application in the CORDIC algorithm.


Think of it this way: if you take 16 steps of CORDIC shift/conditional add,
each one of those adds round-off error. If the computation is done with
16-bit precision, each one adds about one bit of round-off error, and
the error from 16 stages are uncorrelated, the net (rms) error for the
full computation is sqrt(16)*1 bit is 4 bits. So your "16-bit" CORDIC
really only produces an answer that is 12-bit accurate.

I have CORDIC implemented in Verilog, and my test bench measures the
peak and rms error of the computation for a few thousand input vectors.
My data path is 16 bits, the input angle is 18 bits, and my actual test
bench output is

test covers 8205 points, full scale is 26980 bits
peak error 8.68 bits, 0.032 %
rms error 2.09 bits, 0.008 %
PASS

> My another question is how to realize an MAC(multiply-and-accumulate)
> and DAC(divide-and-accumulate) using CORDIC. The paper says they can.
> Although I have read the relevant papers on the website of Ray, I have
> not got the answer. Could you shed some light on this question?


I don't see any relation between MAC/DAC and CORDIC.
Can you quote the relevant section of the paper?
Maybe you misread it.

- Larry
Reply With Quote
  #3 (permalink)  
Old 01-07-2004, 01:25 AM
Jeff
Guest
 
Posts: n/a
Default Re: Questions about guard bits in CORDIC algorithm

Thank you very much.
The paper reads: In addition to the CORDIC vectoring and rotation
modes, Tab. 2 also shows how to elegantly implement the MAC and DAC
(divide-and-accumulate) operations using CORDIC arithmetic:

MAC: yout=yout'+xin*yin,
DAC: xout=xout'+xin/yin


At first, I have the same doubt. But it states clearly.


>
> I don't see any relation between MAC/DAC and CORDIC.
> Can you quote the relevant section of the paper?
> Maybe you misread it.
>
> - Larry

Reply With Quote
  #4 (permalink)  
Old 01-07-2004, 07:55 AM
Ray Andraka
Guest
 
Posts: n/a
Default Re: Questions about guard bits in CORDIC algorithm

I think of guard bits as extra MSBs to prevent overflow. With CORDIC,
worst case you need 2 to accommodate the gain (1.65) plus rotation of the
worst case vector on (45 degree line, full scale I and Q) to a cardinal
axis, which gives a 'gain' of sqrt(2) on one axis. CORDIC also suffers
from some truncation errors at each iteration due to the right shift of
the cross components. If you simply truncate at each iteration, the worst
case error is roughly log2(iterations) bits, which tells you the number of
bits extra you should keep in the LSBs to minimize the trucation error at
the output.

I'm not aware of a multiply-accumulate or divide-accumulate directly,
however the CORDIC can be modified to do multiplication or division and
then it is a simple matter to accumulate the results with an extra adder.
I describe the multiplication and division algorithms for CORDIC in my
CORDIC paper, which I think you have probably seen.

Jeff wrote:

> Hi,
> I have learned about CORDIC from this group, especially from Ray. Now,
> I have several more questions.
> One paper described the implement structure of CORDIC algorithm. It
> uses 16 bits data width and 6 guard bits internally. What is the guard
> bits? I have borrowed several digital design books from library and
> they do not mention that. Even though I can guess guard bits are used
> for overflow prevention, it is far away from understanding the
> utilization of its application in the CORDIC algorithm.
> My another question is how to realize an MAC(multiply-and-accumulate)
> and DAC(divide-and-accumulate) using CORDIC. The paper says they can.
> Although I have read the relevant papers on the website of Ray, I have
> not got the answer. Could you shed some light on this question?
>
> Thans in advance


--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email [email protected]
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759


Reply With Quote
  #5 (permalink)  
Old 01-08-2004, 02:19 AM
Jeff
Guest
 
Posts: n/a
Default Re: Questions about guard bits in CORDIC algorithm

Thank you very much, Ray.
As what you say, I eventurely find that the auther realized multiply
and divide using CORDIC, then add the results from the paper.
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Filtered Back Projection Algorithm (FBP Algorithm) Bapaiah Katepalli Verilog 1 06-23-2006 06:58 PM
Altera Stratix 80: How to divide a bits stream to even bits streamand odd bits stream zhao FPGA 1 12-16-2003 06:45 PM


All times are GMT +1. The time now is 05:42 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved