FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 03-05-2008, 11:59 PM
Fei Liu
Guest
 
Posts: n/a
Default question about verilog language constructs

1. In verilog, for continuous assignment, the assignee must be scalar
or vector net; for procedure assignment, the assignee cannot be scalar
or vector net; then for procedure continuous assignment, the assignee
can only be scalar or vector of registers. This is very confusing. I
can't quite see the logic behind such language design.

2. multiple event triggered always block updating same register
causing race condition or undefined behavior. e.g.

always @(posedge clock)
a = 1'b1;
always @(reset)
a = 1'b0;
If both reset turns high and clock turns high at the same time, what's
the result? I see code like this in text books which confuses me.

3. my understanding is that always statements is similar to
initial
forever statements

other than the practical reason always is preferred for looping
statements, any catch I don't see?

Thanks a lot!

Fei
Reply With Quote
  #2 (permalink)  
Old 03-06-2008, 12:58 AM
Dwayne Dilbeck
Guest
 
Posts: n/a
Default Re: question about verilog language constructs

This question is better to ask on comp.lang.verilog.
1. Yep, very confusing. Thus why with System Verilog, you have new rules
that don't care about where and what is assigned. type "logic" can be
assigned in both flows.

2. That is the point of text book examples. It is supposed to be
confusing. It is an example of what not to do. there are better ways to code
this and know exactly what the result would be. In this case if reset
changed value at the same time that clock had a posedge the final result
would depend on the order that the TOOL executed the blocks. There is no
defined garantee of which value would be written.

3. Logically the initial forever and always blocks appear to be similar. But
you would be hard pressed to find a synthesis tool that will turn a initial
forever construct into logic gates. For emulation there are some synthesis
tools that can map an initial forever block to gates. Another gotcha is when
is the block evaluated. The simulator must schedule events to happen. Based
on the LRM and the tool nvendors interpretation of the LRM the order I which
the initial blocks are evaluated and the always blocks are evaluated will
change the behavior of the simulation.

"Fei Liu" <[email protected]> wrote in message
news:[email protected]m...
> 1. In verilog, for continuous assignment, the assignee must be scalar
> or vector net; for procedure assignment, the assignee cannot be scalar
> or vector net; then for procedure continuous assignment, the assignee
> can only be scalar or vector of registers. This is very confusing. I
> can't quite see the logic behind such language design.
>
> 2. multiple event triggered always block updating same register
> causing race condition or undefined behavior. e.g.
>
> always @(posedge clock)
> a = 1'b1;
> always @(reset)
> a = 1'b0;
> If both reset turns high and clock turns high at the same time, what's
> the result? I see code like this in text books which confuses me.
>
> 3. my understanding is that always statements is similar to
> initial
> forever statements
>
> other than the practical reason always is preferred for looping
> statements, any catch I don't see?
>
> Thanks a lot!
>
> Fei



Reply With Quote
  #3 (permalink)  
Old 03-06-2008, 01:57 AM
Fei Liu
Guest
 
Posts: n/a
Default Re: question about verilog language constructs


> 2. That is the point of text book examples. It is supposed to be
> confusing. It is an example of what not to do. there are better ways to code
> this and know exactly what the result would be. In this case if reset
> changed value at the same time that clock had a posedge the final result
> would depend on the order that the TOOL executed the blocks. There is no
> defined garantee of which value would be written.


Yeah, my point is text book authors should avoid having such kind of
code in examples here and there, except to illustrate this is a bad
coding practice. But what I see is that authors feel it's acceptable
to write code like this. It annoys me.

Reply With Quote
  #4 (permalink)  
Old 03-06-2008, 03:36 AM
lm317t
Guest
 
Posts: n/a
Default Re: question about verilog language constructs

On Mar 5, 7:57 pm, Fei Liu <[email protected]> wrote:
> > 2. That is the point of text book examples. It is supposed to be
> > confusing. It is an example of what not to do. there are better ways to code
> > this and know exactly what the result would be. In this case if reset
> > changed value at the same time that clock had a posedge the final result
> > would depend on the order that the TOOL executed the blocks. There is no
> > defined garantee of which value would be written.

>
> Yeah, my point is text book authors should avoid having such kind of
> code in examples here and there, except to illustrate this is a bad
> coding practice. But what I see is that authors feel it's acceptable
> to write code like this. It annoys me.


Icarus verilog interprets the posedge as "higher priorty" than the
reset changing ([email protected] implies change, not just high or low).

The real question is how does the design compiler interpret this? I
think that rather than writing ambiguous behavioral code for the
design compiler to interpret as the book suggests, write it the
"normal way" as you would want it to synthesize:
always @ (posedge clock or negedge reset)
if you want an active low asynchronous reset.

The academics just want you to understand all corners of the language
I guess.

here's my test code:
//test.v
module counter(out, clk, reset);

parameter WIDTH = 8;

output [WIDTH-1 : 0] out;
input clk, reset;

reg [WIDTH-1 : 0] out;
wire clk, reset;

always @reset
out = 0;

always @(posedge clk)
out = 1;


endmodule // counter

//test_test.v
module test;

/* Make a reset that pulses once. */
reg reset = 0;
initial begin
# 5 reset = 1;
# 10 reset = 0;
# 5 reset = 1;
# 5 reset = 0;
# 100 $finish;
end

/* Make a regular pulsing clock. */
reg clk = 0;
always #5 clk = !clk;

wire [7:0] value;
counter c1 (value, clk, reset);

initial
$monitor("At time %t, reset %h value = %h (%0d)",
$time, reset, value, value);
endmodule // test

and run:
iverilog test.v test_test.v -o test & ./test


Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
IEEE Standard Verilog® Hardware Description Language [LinuxFc4]GaLaKtIkUs™ Verilog 10 09-15-2005 05:39 PM
Mixed language [email protected] Verilog 2 09-08-2005 07:02 AM
most used system verilog constructs tinuashu Verilog 0 01-05-2005 12:46 AM
Verilog standard language or vendor specific? CRW Verilog 0 07-26-2004 07:50 PM
[ANN] Python as a test and modeling language for Verilog Verilog 0 07-15-2004 04:28 PM


All times are GMT +1. The time now is 04:56 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved