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Old 05-29-2009, 03:22 PM
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Default Question about SERR of Xilinx PCIE core.

Hello, I am using the embedded PCIe block in Xilinx V5LX110T. The
wrapper is generated by pcie_blk_plus_v1.10, which includes some block
mems and support read/write to the mem.
I changed the UCF file to match our board. PC can detect the board and
it can be read/written. It seems working except the lspci -vv always
shows the SERR+ in the status report.
It has bothered me many days.
Any idea and recommendation are appreciated.

Thank you very much.
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