On Jul 24, 10:54*am, ghelbig <
[email protected]> wrote:
> On Jul 23, 11:44 am, Mike Treseler <[email protected]> wrote:
>
> > ghelbig wrote:
> > > I haven't entered pin numbers manually in years. *Too easy to make
> > > mistakes, especially with pin counts in the K range.
> > > I have one PERL script that parses a wirelist into a spreadsheet, and
> > > another that turns the spreadsheet into a constraint file.
> > > And Quartus supports Tcl scripts for pin number entry, that method
> > > works "just fine" too.
>
> > That makes good sense for pin numbers.
> > But direction should be inferred from the code,
> > and IO type and timing is a separate problem.
>
> > * * * *-- Mike Treseler
>
> That's why I run it through the spread sheet; I set the I/O type
> there. *Getting direction from the top level would be a good addition.
>
> Timing is always a problem...
>
I use the spreadsheet as basically the 'master' data set and put all I/
O information there. I have columns in there for...
1. The basics: signal name, direction, pin number, setup, hold, clock-
to-output, propogation delay requirements.
2. Device specific options: I/O drive strength, slew rate,
termination, I/O voltage standard, fast input/output registers (and
any other properties that belong with a signal I/O).
Each of the things in #1 and #2 get a column in the spreadsheet. Each
signal gets a row.
Various pages in that spreadsheet workbook produce the following
design artifacts that are then simply copy/pasted into the appropriate
tool. The formulas on those pages produce text in the format required
by the tool (i.e. valid VHDL or TCL).
- Design top level port map (can be pasted into the VHDL file).
- Port map with the connections to the testbench instantiation of the
design.
- TCL script to load into the synthesis tool to set all of the
properties.
Since it's in a spreadsheet I can use formulas so that changes in one
area get reflected in all of the appropriate places. Particularly
when it comes to calculating timing requirements this is useful
because you can have a completely different workbook page that defines
the clocks involved, DLL/PLL clock multiplier/divider values, setup/
hold requirements of the devices that the design will be talking to.
Deriving the timing requirements for the new design in this manner,
makes it a lot clearer to follow (and find calculation errors) than if
the calculations are done 'somewhere else' and only the end result
value is pasted into the tool.
In effect the spreadsheet is the master source of the information and
also directly produces design artifacts that are then copied into
other tools...and I suppose if there is a way to output the values in
the pages of a spreadsheet into separate files then the manual copy/
paste operation could be eliminated.
KJ