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Old 04-18-2006, 07:37 AM
Tommy Thorn
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Default Quartus SignalTap and bus turn around

Quartus SignalTap (and ISE equivalent ChipScope) are a truly awesome
tools, however I ran into something strange.

As part of my design I interface an SRAM (this is the Nios Dev kit,
Cyclone Ed.), and thus have a net like

module main(...
inout wire [31:0] fse_d,
output reg sram_oe_n,
...

reg [31:0] fse_d_out;
assign fse_d = sram_oe_n ? fse_d_out : 32'hZZZZZZZZ;
....

but in the captured data fse_d is shown changing one cycle after
fse_d_out. Is this delay an expected bus turn around associated with a
tristate bus?

Just to be sure I understood this correctly, I added an

wire [7:0] fse_d_out_plus_1 = fse_d_out + 1;

and it does show up as expected, synchronous with fse_d_out, in the trace.

BTW everything, including SignalTap, is synchronized to the same 200 MHz
clock synthesized with a PLL.

Thanks
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Old 04-18-2006, 07:40 AM
Mark McDougall
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Default Re: Quartus SignalTap and bus turn around

Tommy Thorn wrote:

> but in the captured data fse_d is shown changing one cycle after
> fse_d_out. Is this delay an expected bus turn around associated with
> a tristate bus?


When's sram_oe_n changing?

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
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  #3 (permalink)  
Old 04-18-2006, 08:19 AM
Tommy Thorn
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Default Re: Quartus SignalTap and bus turn around

Mark McDougall wrote:
> Tommy Thorn wrote:
>
>> but in the captured data fse_d is shown changing one cycle after
>> fse_d_out. Is this delay an expected bus turn around associated with
>> a tristate bus?

>
> When's sram_oe_n changing?


Good point, I forget to mention that. It's set a cycle earlier than
fse_d_out. However in an experiment I just ran, sram_oe_n was held
constant and the effect was still there, so it has nothing to do with
"bus turn around" but is still related to the external bus.

Puzzled.

Thanks,
Tommy
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