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This question is Quartus II specific but I figured since this would
the proper place to find at least one person with this problem.

I want to use the fixed point package provided here:
http://www.accellera.org/apps/group_...wg_abbrev=vhdl

I can compile the library and use the files, but a problem arises when
I create a schematic file and try to synthesize. To use the fixed
point numbers I have to declare the bus width like so: var_name sfixed
(1 downto -30)

When I create a block out the file and try to synthesize it, I get an
error about illegal bus width "-30". Is there a way to get around
this? Or I cannot use negative numbers as a bus width?

Thanks

"Chico" <[email protected]> wrote in message
news:817c83f5-984d-43c7-9d00-9b5e79f2f581@o30g2000vbc.googlegroups.com...
> This question is Quartus II specific but I figured since this would
> the proper place to find at least one person with this problem.
>
> I want to use the fixed point package provided here:
> http://www.accellera.org/apps/group_...wg_abbrev=vhdl
>
> I can compile the library and use the files, but a problem arises when
> I create a schematic file and try to synthesize.

Don't create a 'schematic file' to synthesize. Just use the VHDL packages
directly. I've used them with Quartus and not had any problems.

KJ

On May 8, 9:04*am, "KJ" <[email protected]> wrote:
> "Chico" <[email protected]> wrote in message
>
> news:817c83f5-984d-43c7-9d00-9b5e79f2f581@o30g2000vbc.googlegroups.com...
>
> > This question is Quartus II specific but I figured since this would
> > the proper place to find at least one person with this problem.
>
> > I want to use the fixed point package provided here:
> >http://www.accellera.org/apps/group_...wg_abbrev=vhdl
>
> > I can compile the library and use the files, but a problem arises when
> > I create a schematic file and try to synthesize.
>
> Don't create a 'schematic file' to synthesize. *Just use the VHDL packages
> directly. *I've used them with Quartus and not had any problems.
>
> KJ

I was thinking of doing that, but I need to assign a PIN to my inputs/
outputs. Is there a way to do that without using a schematic file
through VHDL? I am using Quartus II 8.0.

"Chico" <[email protected]> wrote in message
news:713706ae-f03d-439c-97c5-591e2a804fb1@z19g2000vbz.googlegroups.com...
On May 8, 9:04 am, "KJ" <[email protected]> wrote:
> "Chico" <[email protected]> wrote in message
>
> news:817c83f5-984d-43c7-9d00-9b5e79f2f581@o30g2000vbc.googlegroups.com...
>
> > This question is Quartus II specific but I figured since this would
> > the proper place to find at least one person with this problem.
>
> > I want to use the fixed point package provided here:
> >http://www.accellera.org/apps/group_...wg_abbrev=vhdl
>
> > I can compile the library and use the files, but a problem arises when
> > I create a schematic file and try to synthesize.
>
> Don't create a 'schematic file' to synthesize. Just use the VHDL packages
> directly. I've used them with Quartus and not had any problems.
>
> KJ

I was thinking of doing that, but I need to assign a PIN to my inputs/
outputs. Is there a way to do that without using a schematic file
through VHDL? I am using Quartus II 8.0.


I don't know how VHDL would look, but the following works in Quartus
for Verilog code:

input SYNC_IN /* synthesis altera_chip_pin_lc = "5"*/;
output SYNC_OUT /* synthesis altera_chip_pin_lc = "39"*/;
input SW_2 /* synthesis altera_chip_pin_lc = "18"*/;
input SW_1 /* synthesis altera_chip_pin_lc = "21"*/;
output LED1 /* synthesis altera_chip_pin_lc = "37"*/;
output LED2 /* synthesis altera_chip_pin_lc = "22"*/;

Look in the Help file under Synthesis Attributes

Wade Hassler

On May 8, 6:39 am, Chico <[email protected]> wrote:
> On May 8, 9:04 am, "KJ" <[email protected]> wrote:
>
>
>
> > "Chico" <[email protected]> wrote in message
>
> >news:817c83f5-984d-43c7-9d00-9b5e79f2f581@o30g2000vbc.googlegroups.com...
>
> > > This question is Quartus II specific but I figured since this would
> > > the proper place to find at least one person with this problem.
>
> > > I want to use the fixed point package provided here:
> > >http://www.accellera.org/apps/group_...wg_abbrev=vhdl
>
> > > I can compile the library and use the files, but a problem arises when
> > > I create a schematic file and try to synthesize.
>
> > Don't create a 'schematic file' to synthesize. Just use the VHDL packages
> > directly. I've used them with Quartus and not had any problems.
>
> > KJ
>
> I was thinking of doing that, but I need to assign a PIN to my inputs/
> outputs. Is there a way to do that without using a schematic file
> through VHDL? I am using Quartus II 8.0.

Yes. This is well documented in the manual. And the tutorial. And
in several download-able examples.

AL