FPGA Central

For the Altera people in this group...

One of the things I find really annoying with Quartus II is that
whenever it gives resource counts, like in the final synthesis report
or in the SignalTap configurator, it gives "bits of memory."

The chip has some combination of M512, M4K and MRAM blocks, not "bits
of memory." This makes it very hard to determine what actually going
on, especially so since I've found it hard to get Quartus to use the
9th bit of M4K blocks, even when it should be possible.

It would be a lot nicer to get the counts of actual physical
resources used.

-hpa

[email protected] (H. Peter Anvin) wrote in message news:<[email protected]>...
> For the Altera people in this group...
>
> One of the things I find really annoying with Quartus II is that
> whenever it gives resource counts, like in the final synthesis report
> or in the SignalTap configurator, it gives "bits of memory."

Hi Peter,

The Memory Bits are provided in the Flow Summary section of the Report
File to give a brief design overview, while inside the Report there is
much more detailed information. The Fitter Resource Usage Summary
section probably gives what you are looking for, breaking out exactly
how many M512s, M4Ks and M-RAMs are required. Note that there is a
detailed RAM Summary Report in both the Analysis and Synthesis section
of the report and the Fitter section. These give the details on each
hierarchical block, how many bits they use and how many of each block
type are used.

An important note is that the Fitter RAM Summary may show more blocks
being used than the user would expect. This is because Quartus can
spread the slices of a RAM across multiple blocks if it helps the
design's timing. This is a feature, and if the device memory fills
up, Quartus will pack them as tightly as possible, but is a cause for
some confusion. In the future there will be a message added to the
report clarifying this.

The upcoming release of Quartus will contain improvements in the
reporting of the memory blocks used as part of the Signal Tap II
configuration.

Hope this helps.

- Subroto Datta
Altera Corp.

Followup to: <[email protected] >
By author: [email protected] (Subroto Datta)
In newsgroup: comp.arch.fpga
>
> Hope this helps.
>
> - Subroto Datta
> Altera Corp.

Indeed it does. Thank you!

-hpa

Hi Peter,

I've got one thing to add to Subroto's posting. The reason you don't know
the exact breakdown of blocks before fitting begins is that Quartus is
automatically deciding the best way to pack your memory bits into memory
blocks. This is a very tricky algorithm to get right (getting good packing,
not screwing up performance, etc.) and a few good friends of mine lost half
a year of their life to it. But the result is that our users get the
benefits of the "TriMatrix" memory in Stratix & Stratix II without having to
worry about the details.

That said, you can always force Quartus to use a particular RAM type if you
instantiate an altsyncram directly and specify the RAM_BLOCK_TYPE primitive.
I believe there is also some sort of assignment you can make in the
assignment editor, but I cannot recall the details.

BTW, you should not be having issues with using the 9th bit. Please send me
a design example of you are finding that Quartus is not working the way you
expect it to.

Regards,

Paul Leventis
Altera Corp.

Followup to: <[email protected]>
By author: "Paul Leventis \(at home\)" <[email protected]>
In newsgroup: comp.arch.fpga
>
> BTW, you should not be having issues with using the 9th bit. Please send me
> a design example of you are finding that Quartus is not working the way you
> expect it to.
>

Will do.

-hpa