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Old 05-27-2009, 08:57 PM
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Default Python code accessing the Altera Virtual JTAG instances (via urJTAG)

Hi,

I have just published the code, which accesses the Virtual JTAG instances
in the Altera FPGAs, in the fully Open Source environment (Python+urJTAG).

The archive is available here:
http://groups.google.pl/group/alt.so...acd8b31ea5bd0d

It contains the Python code, and the simple VHDL code, which allows just
enumeration of the Virtual JTAG instances, and then blinking the leds via
the JTAG DR register...

However this code may be easily extended to more serious things...
I hope that someone may find it usefull.
--
BR, Wojtek
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