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Old 03-06-2006, 01:44 PM
Marco
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Default Pullup questions on Spartan3

Hi, Spartan3 does have internal pullup and pulldown resistors on all
its I/O. I'll work with LVCMOS33. I have to communicate with a DSP in a
serial mode both during configuration (master serial) and while working
after the FPGA has been programmed. I was supposed to bring the CCLK
(clock during configuration) and the serial_clock signals from the FPGA
on an AND port in order to use the same pin of the DSP for the clock in
the 2 situations. Could I set low the HSWAP_EN during configuration to
pullup the serial_clock (which is on a user pin, global clock) and
then, after its completition, bring the CCLK at a high logic level with
the CclkPin Bitstream option? Do these setting use internal pullups?
When can I use a internal pullup and when should I place an external
one?
Thanks, Marco

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Old 03-06-2006, 02:02 PM
Gabor
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Default Re: Pullup questions on Spartan3


Marco wrote:
> Hi, Spartan3 does have internal pullup and pulldown resistors on all
> its I/O. I'll work with LVCMOS33. I have to communicate with a DSP in a
> serial mode both during configuration (master serial) and while working
> after the FPGA has been programmed. I was supposed to bring the CCLK
> (clock during configuration) and the serial_clock signals from the FPGA
> on an AND port in order to use the same pin of the DSP for the clock in
> the 2 situations. Could I set low the HSWAP_EN during configuration to
> pullup the serial_clock (which is on a user pin, global clock) and
> then, after its completition, bring the CCLK at a high logic level with
> the CclkPin Bitstream option? Do these setting use internal pullups?
> When can I use a internal pullup and when should I place an external
> one?
> Thanks, Marco


Generally it's better to use an external pullup resistor when you need
to be sure of the logic value external to the FPGA. The internal
pullups
are normally just strong enough to guarantee the state of a non-
connected pin. That being said I've noticed that the pullups at least
on Virtex 2 can be quite strong, enough to pull up an external net to
other CMOS loads.

The HSWAP_EN pin only controls the pullup on CCLK until the
configuration starts. The bitstream option normally takes over
as soon as the value is read in near the beginning of the bitstream.
I'm assuming that by this point something should be driving the
CCLK pin if you use serial configuration, either the FPGA itself
in master serial mode or some external source in slave serial
mode, so the pullup option for CCLK in this case really takes
effect when configuration is complete. If you use the master
configuration mode you need to look into the final state of the
CCLK pin at the end of configuration. The diagrams in the datasheet
don't show this, but if the CCLK in fact ends in a low state, you
will have a very slow rising clock edge when the CCLK pin reverts
to tristate with a weak pullup.

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Old 03-06-2006, 02:45 PM
Marco
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Default Re: Pullup questions on Spartan3

Gabor, HSWAP_EN controls the pullup on the I/Os during configuration
and in this stage I want to have the CCLK (configuration clock,
dedicated pin) working, while the serial_clock (another pin used after
initialization for serial communication with the DSP) has to be set to
a high logic level at the AND port. Then, when all done and the FPGA
has been programmed, I need the CCLK to be high and the serial_clock to
be enabled, so that in both situations I get the correct clock out from
the AND port and going into the same pin of the DSP.
Do I need external pullups for that?
Thanks, Marco

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  #4 (permalink)  
Old 03-06-2006, 07:06 PM
Peter Alfke
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Default Re: Pullup questions on Spartan3

Marco, why do you not just put in the external pull-up resistor and
figure out later whether it is redundant?
A resistor costs almost nothing, and takes very little room.
I suggest to worry about more important things. Maybe I am just
pragmatic...
Peter Alfke

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Old 03-06-2006, 08:59 PM
Marco
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Default Re: Pullup questions on Spartan3

Peter, yours seems a good suggestion, I was just wondering how and when
to use internal pullups or pulldowns.
Marco

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  #6 (permalink)  
Old 03-06-2006, 09:59 PM
Peter Alfke
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Default Re: Pullup questions on Spartan3

Internal pull-up resistors are meant to provide a defined High on the
unbonded or unused pin. They have also been (ab)used to form a "wired
OR" (=wiredAND), which you seem to have in mind. But the wide variation
of the internal resistor value (sometimes even outside the very loose
specification) have given these tricks a bad name. You do not want to
get into hard-to-find crosstalk issues, for the lack of penny-resistor
!
Peter Alfke, Xilinx Applications.

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  #7 (permalink)  
Old 03-06-2006, 10:03 PM
Jim Granville
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Default Re: Pullup questions on Spartan3

Marco wrote:
> Peter, yours seems a good suggestion, I was just wondering how and when
> to use internal pullups or pulldowns.
> Marco


Don't forget that internal Pullups/Pulldowns in FPGAs that are
configurable, will usually be undefined during load : ie they are
Time Conditional. If your system relies on the pullup during non-operate
states, then external pullups are the safest.

-jg

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  #8 (permalink)  
Old 03-07-2006, 07:49 AM
Marco
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Default Re: Pullup questions on Spartan3

Thanks, I'll go with external pullups, ok.
Marco

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