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  #1 (permalink)  
Old 09-26-2003, 08:30 AM
Max
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Posts: n/a
Default pullup on inputs

I use xilinx ise webpack 6.1 sp1.
In may project I tried to add contrains like:

NET "probes<0><0>" LOC = "D11" | PULLUP ;
NET "probes<0><1>" LOC = "D12" | PULLUP ;
NET "probes<0><2>" LOC = "C12" | PULLUP ;

This signals are all input.

In translate report is reported:

Attached a PULLUP primitive to pad net probes<0><2>
Attached a PULLUP primitive to pad net probes<0><1>
Attached a PULLUP primitive to pad net probes<0><0>


But in place&route report there is no reference to pullups:
Resolved that IOB <probes<0><0>> must be placed at site D11.
Resolved that IOB <probes<0><1>> must be placed at site D12.
Resolved that IOB <probes<0><2>> must be placed at site C12.

Even in pad report is not mentioned pullup resistor for that signals.

How can I be sure about the presence of pullup resistors on that ports?

thanks
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  #2 (permalink)  
Old 09-26-2003, 09:06 AM
Allan Herriman
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Default Re: pullup on inputs

On 26 Sep 2003 00:30:38 -0700, [email protected] (Max) wrote:

>I use xilinx ise webpack 6.1 sp1.
>In may project I tried to add contrains like:
>
>NET "probes<0><0>" LOC = "D11" | PULLUP ;
>NET "probes<0><1>" LOC = "D12" | PULLUP ;
>NET "probes<0><2>" LOC = "C12" | PULLUP ;
>
>This signals are all input.
>
>In translate report is reported:
>
>Attached a PULLUP primitive to pad net probes<0><2>
>Attached a PULLUP primitive to pad net probes<0><1>
>Attached a PULLUP primitive to pad net probes<0><0>
>
>
>But in place&route report there is no reference to pullups:
>Resolved that IOB <probes<0><0>> must be placed at site D11.
>Resolved that IOB <probes<0><1>> must be placed at site D12.
>Resolved that IOB <probes<0><2>> must be placed at site C12.
>
>Even in pad report is not mentioned pullup resistor for that signals.
>
>How can I be sure about the presence of pullup resistors on that ports?


Didn't you just ask this question in comp.lang.vhdl?

There are a number of ways:

1. Get a better version of the software, which will allow you to use
fpga_editor to view the configuration of the pin.

2. Use ngd2vhdl (or whatever) to generate a human readable version of
the chip contents. I *think* that this will include the pullup if
it's there.

3. Download the bitstream into an fpga and measure the electrical
characteristics on a curve tracer, multimeter, or whatever test
equipment comes to hand.

Allan.
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  #3 (permalink)  
Old 09-26-2003, 10:17 AM
Amontec Team
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Posts: n/a
Default Re: pullup on inputs

Max wrote:
> I use xilinx ise webpack 6.1 sp1.
> In may project I tried to add contrains like:
>
> NET "probes<0><0>" LOC = "D11" | PULLUP ;
> NET "probes<0><1>" LOC = "D12" | PULLUP ;
> NET "probes<0><2>" LOC = "C12" | PULLUP ;
>
> This signals are all input.
>
> In translate report is reported:
>
> Attached a PULLUP primitive to pad net probes<0><2>
> Attached a PULLUP primitive to pad net probes<0><1>
> Attached a PULLUP primitive to pad net probes<0><0>
>
>
> But in place&route report there is no reference to pullups:
> Resolved that IOB <probes<0><0>> must be placed at site D11.
> Resolved that IOB <probes<0><1>> must be placed at site D12.
> Resolved that IOB <probes<0><2>> must be placed at site C12.
>
> Even in pad report is not mentioned pullup resistor for that signals.
>
> How can I be sure about the presence of pullup resistors on that ports?
>
> thanks

In your constraint file (.ucf) add the following lines to add pull-up:


################################################## ##############################
## PULLUP DESCRIPTION (IF NEEDED)
################################################## ##############################
NET your_netname PULLUP;

It works well !

Laurent
www.amontec.com
______________________________________________
Amontec provides new low cost solutions
for FPGA Download and Processor Debug

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  #4 (permalink)  
Old 09-26-2003, 10:18 AM
Amontec Team
Guest
 
Posts: n/a
Default Re: pullup on inputs

Max wrote:

> I use xilinx ise webpack 6.1 sp1.
> In may project I tried to add contrains like:
>
> NET "probes<0><0>" LOC = "D11" | PULLUP ;
> NET "probes<0><1>" LOC = "D12" | PULLUP ;
> NET "probes<0><2>" LOC = "C12" | PULLUP ;
>
> This signals are all input.
>
> In translate report is reported:
>
> Attached a PULLUP primitive to pad net probes<0><2>
> Attached a PULLUP primitive to pad net probes<0><1>
> Attached a PULLUP primitive to pad net probes<0><0>
>
>
> But in place&route report there is no reference to pullups:
> Resolved that IOB <probes<0><0>> must be placed at site D11.
> Resolved that IOB <probes<0><1>> must be placed at site D12.
> Resolved that IOB <probes<0><2>> must be placed at site C12.
>
> Even in pad report is not mentioned pullup resistor for that signals.
>
> How can I be sure about the presence of pullup resistors on that ports?
>
> thanks


Hi,

In your constraint file (.ucf) add the following lines to add pull-up:


################################################## ##############################
## PULLUP DESCRIPTION (IF NEEDED)
################################################## ##############################
NET your_netname PULLUP;

It works well !

Laurent
www.amontec.com
______________________________________________
Amontec provides new low cost solutions
for FPGA Download and Processor Debug

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  #5 (permalink)  
Old 09-26-2003, 04:40 PM
John_H
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Posts: n/a
Default Re: pullup on inputs

If your syntax does work, you can see the pullup in the FPGA Editor for your
Placed & Routed design. Find one of the IOBs, double click on the IOB and
you'll get a pop-up for just that cell. Included are checkboxes for some of
the IOB options including logic standard, fast/slow, and pullup. If the
pullup isn't indicated *there* it isn't in your finalized design.


"Max" <[email protected]> wrote in message
news:[email protected] om...
> I use xilinx ise webpack 6.1 sp1.
> In may project I tried to add contrains like:
>
> NET "probes<0><0>" LOC = "D11" | PULLUP ;
> NET "probes<0><1>" LOC = "D12" | PULLUP ;
> NET "probes<0><2>" LOC = "C12" | PULLUP ;
>
> This signals are all input.
>
> In translate report is reported:
>
> Attached a PULLUP primitive to pad net probes<0><2>
> Attached a PULLUP primitive to pad net probes<0><1>
> Attached a PULLUP primitive to pad net probes<0><0>
>
>
> But in place&route report there is no reference to pullups:
> Resolved that IOB <probes<0><0>> must be placed at site D11.
> Resolved that IOB <probes<0><1>> must be placed at site D12.
> Resolved that IOB <probes<0><2>> must be placed at site C12.
>
> Even in pad report is not mentioned pullup resistor for that signals.
>
> How can I be sure about the presence of pullup resistors on that ports?
>
> thanks



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  #6 (permalink)  
Old 09-30-2003, 08:28 AM
Max
Guest
 
Posts: n/a
Default Re: pullup on inputs

"John_H" <[email protected]> wrote in message news:<[email protected]>...

> If your syntax does work, you can see the pullup in the FPGA Editor for your
> Placed & Routed design. Find one of the IOBs, double click on the IOB and
> you'll get a pop-up for just that cell. Included are checkboxes for some of
> the IOB options including logic standard, fast/slow, and pullup. If the
> pullup isn't indicated *there* it isn't in your finalized design.

What is "FPGA Editor"? I tried with Floorplanner ("View/Edit Placed
Design") but if I double click the iob no pupup is opened.
Which tool I need to use?

thanks
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  #7 (permalink)  
Old 09-30-2003, 04:18 PM
John_H
Guest
 
Posts: n/a
Default Re: pullup on inputs

Xilinx ISE - the not-free version of the tools - has the FPGA Editor, listed
inter the "Place & Route" section of the design implementation as "View/Edit
Routed Desing (FPGA Editor)."

I hear WebPack doesn't have this tool which gives the low-level visibility
an engineer might want in order to understand how the tools are implementing
the design.

The "Pad Report" is the third item on my Place & Route list.
Double-clicking there produced a file that's ready to import to a
spreadsheet. It's not terribly readable in the ISE window (includes
delimiters, not spaces) but does include Pullup/PullDown information.


"Max" <[email protected]> wrote in message
news:[email protected] om...
> "John_H" <[email protected]> wrote in message

news:<[email protected]>...
>
> > If your syntax does work, you can see the pullup in the FPGA Editor for

your
> > Placed & Routed design. Find one of the IOBs, double click on the IOB

and
> > you'll get a pop-up for just that cell. Included are checkboxes for

some of
> > the IOB options including logic standard, fast/slow, and pullup. If the
> > pullup isn't indicated *there* it isn't in your finalized design.

> What is "FPGA Editor"? I tried with Floorplanner ("View/Edit Placed
> Design") but if I double click the iob no pupup is opened.
> Which tool I need to use?
>
> thanks



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  #8 (permalink)  
Old 11-01-2003, 02:38 AM
Pete Dudley
Guest
 
Posts: n/a
Default Re: pullup on inputs

The map report is the easiest place to verify that you've gotten your
pullups. It has a section like this. Look under Resistor.


+---------------------------------------------------------------------------
---------------------------------------------+
| IOB Name | Type | Direction | IO Standard |
Drive | Slew | Reg (s) | Resistor | IOB |
| | | | |
Strength | Rate | | | Delay |
+---------------------------------------------------------------------------
---------------------------------------------+
| diff_clk_out | DIFFM | OUTPUT | LVPECL_33 |
| | OUTDDR | | |
| diffclk_in | DIFFM | INPUT | LVDS_33 |
| | | | |
| clk_in | IOB | INPUT | LVTTL |
| | | | |
| led<0> | IOB | OUTPUT | LVTTL |
12 | SLOW | | | |
| led<1> | IOB | OUTPUT | LVTTL |
12 | SLOW | | | |
| led_b<0> | IOB | OUTPUT | LVTTL |
12 | SLOW | | | |
| led_b<1> | IOB | OUTPUT | LVTTL |
12 | SLOW | | | |
| push1 | IOB | INPUT | LVTTL |
| | | PULLUP | |
| reset_n | IOB | INPUT | LVTTL |
| | | | |
| uled | IOB | OUTPUT | LVTTL |
12 | SLOW | | | |
+---------------------------------------------------------------------------
--------------------------------------------
"Max" <[email protected]> wrote in message
news:[email protected] om...
> I use xilinx ise webpack 6.1 sp1.
> In may project I tried to add contrains like:
>
> NET "probes<0><0>" LOC = "D11" | PULLUP ;
> NET "probes<0><1>" LOC = "D12" | PULLUP ;
> NET "probes<0><2>" LOC = "C12" | PULLUP ;
>
> This signals are all input.
>
> In translate report is reported:
>
> Attached a PULLUP primitive to pad net probes<0><2>
> Attached a PULLUP primitive to pad net probes<0><1>
> Attached a PULLUP primitive to pad net probes<0><0>
>
>
> But in place&route report there is no reference to pullups:
> Resolved that IOB <probes<0><0>> must be placed at site D11.
> Resolved that IOB <probes<0><1>> must be placed at site D12.
> Resolved that IOB <probes<0><2>> must be placed at site C12.
>
> Even in pad report is not mentioned pullup resistor for that signals.
>
> How can I be sure about the presence of pullup resistors on that ports?
>
> thanks



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