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Old 04-13-2006, 12:54 AM
Eli Billauer
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Default Published Verilog code: Timing improvement and FWFT FIFOs


I'd just like to announce, that I've published three Verilog modules,
which use a common FIFO to create another, modified FIFO. These modules
are actually wrappers.

There are two objectives for this:

1. Improving timing by putting registers on rd_en and dout, while
presenting the same signal interface to the design which uses the
wrapped FIFO. In other words, if a FIFO becomes involved in critical
paths, this could be a quick solution (at the cost of some extra
2. Using a regular FIFO to make a FWFT (First Word Fall Through) FIFO.

I wrote these wrappers as a result of abandoning the Virtex-4's FIFO16,
being left with sliced-based FIFO's, which were too slow.

The material can be found at http://www.billauer.co.il/reg_fifo.html


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