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Old 01-18-2005, 12:34 AM
michel leconte
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Default Problems in timing simulations

Thank you Ken,

your're right, I didn't adapted the data transitions relatively to the edge
of my clock in the testbench. Now, during the simulations the violations
has disappeared and the design responds has desired.

Another question when you say :

"I had the same problems in modelsim and solved it by making the testbench
wait for a 1/4 clock period after an edge before supplying the next input.
You may need to reflect your real system more closely than 1/4 clock period
if you have detailed timing specs."

Does it mean that your design has an offset in constraint equal to
1/4 of the period clock ?


Michel
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Old 01-18-2005, 09:48 AM
Ken
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Default Re: Problems in timing simulations

Hi Michel,

> Another question when you say :
>
> "I had the same problems in modelsim and solved it by making the testbench
> wait for a 1/4 clock period after an edge before supplying the next input.
> You may need to reflect your real system more closely than 1/4 clock
> period
> if you have detailed timing specs."
>
> Does it mean that your design has an offset in constraint equal to
> 1/4 of the period clock ?


No - the design I was working on was not destined for actual hardware so I
simply used 1/4 of the clock period as a suitable value as a time buffer
between my clock edges and input data transitions.

I had a half_clock_period generic in my testbench and so I could simply say
for example:

wait until rising_edge(CLK);
wait for HALF_CLOCK_PERIOD/2;
-- supply new data now

To avoid the setup errors from the simulator.

If I had more detailed timing information relating to data coming from a
device upstream of the FPGA I would have to been more diligent with how long
I waited after each clock edge.....

Cheers,

Ken




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