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Old 01-16-2005, 11:36 PM
michel leconte
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Default Problems in timing simulations

Hi all,

I work with ISE.6.3.3i and ModelSim 5.8c
the target is a Virtex II Pro 70 -6.


My design has been P&R for two frequencies : 50 MHz and 80MHz.

In this two cases, the timing report indicates no errors and all the
timing
constraints were achieved. The timing constraints are essentially a
PERIOD constraint and several FROM TO (all pads <-> all FF, all pads
<-> all RAM, all FF <-> all RAM).

But at timing simulation, some differences appear.

At the lower frequency, the design responds well to the stimuli and
they were no warnings.

At 80 MHz, after my reset phasis, I see two kinds of warnings :

1. X_FF SETUP Low VIOLATION ON I WITH RESPECT TO CLK
2. X_FF HOLD High VIOLATION ON I WITH RESPECT TO CLK

appearing at each period of the simulation and the outputs of my
design aren't defined (all reds)..

My problem is that the timing report detects no errors so I don't know
where to search.

Does somebody has an advice to resolve these warnings
or pointers to have more informations about SETUP TIMING
or HOLD TIMING ???

thank you very much for your help.

Michel
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  #2 (permalink)  
Old 01-17-2005, 12:03 AM
Jeremy Stringer
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Default Re: Problems in timing simulations

> My design has been P&R for two frequencies : 50 MHz and 80MHz.
> In this two cases, the timing report indicates no errors and all the
> timing


Just to clarify, you have synthesised/placed and routed twice, with
different constraints, generating a 50MHz capable design, and a 80MHz
capable design? i.e You aren't mixing the 50MHz and 80MHz clocks in one
design?

Jeremy
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  #3 (permalink)  
Old 01-17-2005, 01:44 AM
Jeremy Stringer
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Default Re: Problems in timing simulations

> My design has been P&R for two frequencies : 50 MHz and 80MHz.
> In this two cases, the timing report indicates no errors and all the
> timing



Just to clarify, you have synthesised/placed and routed twice, with
different constraints, generating a 50MHz capable design, and a 80MHz
capable design? i.e You aren't mixing the 50MHz and 80MHz clocks in one
design?

Jeremy
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  #4 (permalink)  
Old 01-17-2005, 09:22 AM
Ken
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Default Re: Problems in timing simulations

> At 80 MHz, after my reset phasis, I see two kinds of warnings :
>
> 1. X_FF SETUP Low VIOLATION ON I WITH RESPECT TO CLK
> 2. X_FF HOLD High VIOLATION ON I WITH RESPECT TO CLK
>
> appearing at each period of the simulation and the outputs of my
> design aren't defined (all reds)..
>
> My problem is that the timing report detects no errors so I don't know
> where to search.
>
> Does somebody has an advice to resolve these warnings
> or pointers to have more informations about SETUP TIMING
> or HOLD TIMING ???


Make sure that in your testbench you are not toggling input signals too
close to your clock edges.

Since you are doing a post par timing simulation (using an sdf file or
similar I assume?) your TB must reflect the real world more closely and
ensure that a suitable time-gap is present between clock edges and your
input signal transitions.

I had the same problems in modelsim and solved it by making the testbench
wait for a 1/4 clock period after an edge before supplying the next input.
You may need to reflect your real system more closely than 1/4 clock period
if you have detailed timing specs.

HTH,

Ken


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  #5 (permalink)  
Old 01-18-2005, 07:10 PM
glen herrmannsfeldt
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Default Re: Problems in timing simulations

michel leconte wrote:

(snip)

> My design has been P&R for two frequencies : 50 MHz and 80MHz.


> In this two cases, the timing report indicates no errors
> and all the timing constraints were achieved.


(snip)

> But at timing simulation, some differences appear.
> At the lower frequency, the design responds well to the stimuli and
> they were no warnings.


> At 80 MHz, after my reset phasis, I see two kinds of warnings :


> 1. X_FF SETUP Low VIOLATION ON I WITH RESPECT TO CLK
> 2. X_FF HOLD High VIOLATION ON I WITH RESPECT TO CLK


(snip)

Setup time is how long the signal must be stable before the CLK
edge, hold time is how long it must be stable after. Either can
be negative but the sum must be positive.

Setup violations can occur from running a design at too high a
clock rate, but normally not hold violations. (That is, for a
synchronous design with one clock.)

As others have indicated, it is likely that you are violating
the constraints on the input. If your logic family doesn't have
zero hold time, you can't change the logic inputs on the clock
edge. Easiest is to change them on the opposite clock edge to
the one used by the FFs.

-- glen

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