> I have performed a functional simulation and static timing analysis
> of my design. Both are OK.
> But when trying to perform timing simulation my state machine
> does not change from the first state.
> What could go wrong?
If you are using the Xilinx ISE tools, then the post-map and post-PAR
simulation models will model the "power-on reset" of the
FPGA for you
automatically (this is completely separate from any user-defined reset
signal you might have in your design).
When you generate the simulation models, there is a setting called "Reset On
Configuration Pulse width" which defines how long (in nanoseconds) the
synchronous elements will wait in their "INIT" states before responding to
clock edges. So, it could be that you just need to make your testbench wait
for a few hundred nanoseconds before doing anything (or reduce the value of
this pulse width when you create the model).
Hope this helps,
-Ben-