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  #1 (permalink)  
Old 07-07-2005, 12:30 PM
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Default Problems with Timing Simulation

Hi,

I have performed a functional simulation and static timing analysis
of my design. Both are OK.

But when trying to perform timing simulation my state machine
does not change from the first state.

I have an external asychronous Reset which I sychronize ...
In the following code "Rst90_n" is the synchronized Reset.
What could go wrong?

PROCESS(Rst90_n, Clk90)
BEGIN
IF Rst90_n='0' THEN
ls_ddr_state <= s_ini_a;
...

ELSIF rising_edge(Clk90) THEN
ls_ddr_state <= next_ls_ddr_state;
...
END IF;
END PROCESS;

PROCESS( ls_ddr_state,...)


BEGIN
next_ls_ddr_state <= ls_ddr_state;
...


CASE ls_ddr_state IS

WHEN s_ini_a => next_ls_ddr_state <= s_ini_b;
next_ls_ddr_csn <= '1';
WHEN s_ini_b => next_ls_ddr_state <= s_ini_c;
next_ls_ddr_csn <= '1';
WHEN s_ini_c => next_ls_ddr_state <= s_ini_d;
next_ls_ddr_csn <= '1';
WHEN s_ini_d => next_ls_ddr_state <= s_init0;
next_ls_ddr_csn <= '1';
WHEN s_init0 =>
-- first actions
...

END CASE;
END PROCESS;

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  #2 (permalink)  
Old 07-07-2005, 01:51 PM
Ben Jones
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Default Re: Problems with Timing Simulation

> I have performed a functional simulation and static timing analysis
> of my design. Both are OK.
> But when trying to perform timing simulation my state machine
> does not change from the first state.
> What could go wrong?


If you are using the Xilinx ISE tools, then the post-map and post-PAR
simulation models will model the "power-on reset" of the FPGA for you
automatically (this is completely separate from any user-defined reset
signal you might have in your design).

When you generate the simulation models, there is a setting called "Reset On
Configuration Pulse width" which defines how long (in nanoseconds) the
synchronous elements will wait in their "INIT" states before responding to
clock edges. So, it could be that you just need to make your testbench wait
for a few hundred nanoseconds before doing anything (or reduce the value of
this pulse width when you create the model).

Hope this helps,

-Ben-


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  #3 (permalink)  
Old 07-07-2005, 02:39 PM
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Default Re: Problems with Timing Simulation

Hi Ben,

thank you for your answer.

I am using Lattice ispLEVER 5.0 together with Modelsim.

What do you mean with "that you just need to make your testbench wait
for a few hundred nanoseconds before doing anything". ?

After deasserting my reset signal in the testbench, my FSM enters the
state
s_ini_a. After three clock cycles the first action occurs in the FSM.
So how can I wait for a few hundred nanoseconds ? With some kind of
enable signal ?

Rgds
André


Ben Jones schrieb:
> > I have performed a functional simulation and static timing analysis
> > of my design. Both are OK.
> > But when trying to perform timing simulation my state machine
> > does not change from the first state.
> > What could go wrong?

>
> If you are using the Xilinx ISE tools, then the post-map and post-PAR
> simulation models will model the "power-on reset" of the FPGA for you
> automatically (this is completely separate from any user-defined reset
> signal you might have in your design).
>
> When you generate the simulation models, there is a setting called "ResetOn
> Configuration Pulse width" which defines how long (in nanoseconds) the
> synchronous elements will wait in their "INIT" states before responding to
> clock edges. So, it could be that you just need to make your testbench wait
> for a few hundred nanoseconds before doing anything (or reduce the value of
> this pulse width when you create the model).
>
> Hope this helps,
>
> -Ben-


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  #4 (permalink)  
Old 07-07-2005, 03:54 PM
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Default Re: Problems with Timing Simulation

I have added an Enable which gets active after some hundred nanoseconds
and
the Timing Simulation is OK now )

One further question:
Are the synchronous elements in the real design immediately ready when
leaving
Global Reset (Pll is already locked) ? Or is there some "wait" time
according to the
timing simulation?

Thank you for your help.

Rgds
André

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  #5 (permalink)  
Old 07-07-2005, 04:01 PM
Ben Jones
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Default Re: Problems with Timing Simulation

Hi Andre,

> I am using Lattice ispLEVER 5.0 together with Modelsim.


Aha. I'm afraid I don't know anything about that! :-)

> What do you mean with "that you just need to make your testbench wait
> for a few hundred nanoseconds before doing anything". ?
> After deasserting my reset signal in the testbench, ...


Well, how does your testebench know how long to wait before deasserting that
reset signal? If you're using VHDL then you might have a "wait for"
statement somewhere, which you can modify appropriately. If you're using
Verilog... well, I don't know anything about that either, I'm afraid.

Of course, as you're using Lattice's tools then there's a very good chance
that nothing I've suggested can help you - sorry!

Cheers,

-Ben-


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  #6 (permalink)  
Old 07-07-2005, 04:27 PM
Ben Jones
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Default Re: Problems with Timing Simulation

Hi Andre,

Interesting to know that the Lattice simulations models work just like the
Xilinx ones in this respect.

> Are the synchronous elements in the real design immediately ready when
> leaving Global Reset (Pll is already locked) ? Or is there some "wait"

time
> according to the timing simulation?


They are ready immediately. The "wait" time is really just an artefact of
the simulation environment. It may be possible when generating your
simulation model to pull the "configuration reset" signal out and turn it
into a port on the model, so that you can control exactly when it gets
de-asserted (relative to other devices in your simulation, for example).
However as I mentioned, I've not used the Lattice tools so I'm guessing a
bit here!

Glad you got it all working.

-Ben-


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  #7 (permalink)  
Old 07-08-2005, 09:04 AM
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Posts: n/a
Default Re: Problems with Timing Simulation

Thanks again for your help.

)

Andre

Ben Jones schrieb:
> Hi Andre,
>
> Interesting to know that the Lattice simulations models work just like the
> Xilinx ones in this respect.
>
> > Are the synchronous elements in the real design immediately ready when
> > leaving Global Reset (Pll is already locked) ? Or is there some "wait"

> time
> > according to the timing simulation?

>
> They are ready immediately. The "wait" time is really just an artefact of
> the simulation environment. It may be possible when generating your
> simulation model to pull the "configuration reset" signal out and turn it
> into a port on the model, so that you can control exactly when it gets
> de-asserted (relative to other devices in your simulation, for example).
> However as I mentioned, I've not used the Lattice tools so I'm guessing a
> bit here!
>
> Glad you got it all working.
>
> -Ben-


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