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Old 04-21-2006, 09:25 AM
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Default problem with shift operation

I hav the follwoing simple code which does left shifting operation.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity counter is
port (
q: inout STD_LOGIC_VECTOR (3 downto 0);
clock: in STD_LOGIC;
reset: in STD_LOGIC;
en: in STD_LOGIC
);
end counter;



architecture counter of counter is
signal count:std_logic_vector(3 downto 0):="0000";
begin

process(clock,reset)
begin

if reset='0' then
count<="0000";
elsif(clock='1') then
if en='1' then

l1: for i in 1 to 3 loop
count(i)<=q(i-1);
end loop l1;
count(0)<='0';

else
count<=q;
end if;
end if;
q<=count; -- The q value is not getting updated with the count
value.
end process;

end counter;

The problem with this code is that the q(port) value is not getting
updated with count value,though count gets updated.I did single step
execution,i see the statement q<=count being executed.I used the tool
Active HDL 4.2.PLEASE HELP....

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  #2 (permalink)  
Old 04-21-2006, 10:20 AM
Kantha
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Default Re: problem with shift operation

Hi,
Instead of declaring count as signal , you declare it as variable and
check out. I think it should work. Normally the signal gets updated at
the end of the process. The use of variable is best suited for your
case.
Regards,
Srikanth

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