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Old 05-08-2009, 02:47 AM
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Default problem during port mapping

hi all,
i wanted to port map a single bit of type std_logic_vector to a
single port of type std_logic but faced difficulty in doing so. is
this actually possible. if yes please give me some suggestions.
any suggestions would be highly appreciated.
thank you
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Old 05-08-2009, 04:08 AM
KJ
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Default Re: problem during port mapping


<[email protected]> wrote in message
news:[email protected]m...
> hi all,
> i wanted to port map a single bit of type std_logic_vector to a
> single port of type std_logic but faced difficulty in doing so. is
> this actually possible. if yes please give me some suggestions.
> any suggestions would be highly appreciated.
> thank you


If 'some_vec' is the std_logic_vector inside the component and 'some_bit' is
the std_logic that you're trying to connect to one of the bits of the vector
(assuming it to be bit 0 here) then...
zz : entity work.blah port map(some_vec(0) => some_bit)

If it is the other way around then...
zz : entity work.blah port map(some_bit => some_vec(0))

KJ


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