FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 05-02-2006, 02:33 PM
GaLaKtIkUs™
Guest
 
Posts: n/a
Default Problem with DCM simulation models

Hi all, I have the following problem:
I have a Virtex-4 Board (ML403). The Virtex-4 is ES. To use the DCM I
have to add the following line to the UCF file : CONFIG STEPPING =
"ES";
The problem is that if I do this the simulation doesn't work (the DCM
never locks).

Cheers

Reply With Quote
  #2 (permalink)  
Old 06-12-2006, 07:03 PM
Guest
 
Posts: n/a
Default Re: Problem with DCM simulation models

Try setting your simulation resolution to ps vice ns.
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
problem with timing simulation (clear explanation of problem) [email protected] FPGA 1 12-06-2005 12:50 PM
How to view internal signals in post synthesis simulation models (Xilinx ISE) thomasc Verilog 0 06-13-2005 03:18 AM
Post-map simulation models Preben Holm FPGA 1 03-20-2005 11:35 AM
VHDL simulation models from Alliance Semiconductors ALuPin FPGA 0 04-27-2004 11:47 AM


All times are GMT +1. The time now is 07:31 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved