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02-08-2008, 11:53 AM

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Problem in assignment of pins in PACE

Hi all,

I have recently just generated HDL netlist from System Generator 9.1
and I have began assigning the pins in PACE for my design.

Although I have assigned most pins as well as the clk, I have problem
understanding how should I assign the last pin 'ce' which is the clock
enable. Do I assign it as an IO pin or is there any constraint as to
how to assign it? Thank you for any helpful comments .

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