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Old 11-20-2007, 08:23 AM
techG
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Default problem with adding custom logic to an IP core (xilinx edk)

Hi all, I'm experiencing problems with adding custom logic to an IP
core that I have generate in EDK. I changed the vhdl file of an auto-
generated IP core that is connected via FSL to the FPGA, but the
behaviour of the program remains still the same. I've tried also to re-
import the modified core to the project, but I still get errors due to
the fact that the file xparameters.h doesn't contains the appropriated
names.
How can I do to let EDK notice changes in vhdl files?
Thank you in advance!

Giulio
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  #2 (permalink)  
Old 11-20-2007, 08:39 AM
Andrew Greensted
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Default Re: problem with adding custom logic to an IP core (xilinx edk)

techG wrote:
> Hi all, I'm experiencing problems with adding custom logic to an IP
> core that I have generate in EDK. I changed the vhdl file of an auto-
> generated IP core that is connected via FSL to the FPGA, but the
> behaviour of the program remains still the same. I've tried also to re-
> import the modified core to the project, but I still get errors due to
> the fact that the file xparameters.h doesn't contains the appropriated
> names.
> How can I do to let EDK notice changes in vhdl files?
> Thank you in advance!
>
> Giulio


Hi Giulio,

You can regenerate the xparameters.h file using this menu option:
Software -> Generate Libraries and BSPs

Andy
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  #3 (permalink)  
Old 11-20-2007, 12:58 PM
Jeff Cunningham
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Default Re: problem with adding custom logic to an IP core (xilinx edk)

techG wrote:
> How can I do to let EDK notice changes in vhdl files?


project -> clean all generated files

OR

hardware -> clean hardware

should do the trick.
-Jeff
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  #4 (permalink)  
Old 11-20-2007, 06:10 PM
Matthew Hicks
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Default Re: problem with adding custom logic to an IP core (xilinx edk)

I just asked this question a couple of days ago. For the complete answer
and process, refer to my "EDK 9.1 Issues" post from 11-15-07.


---Matthew Hicks


> Hi all, I'm experiencing problems with adding custom logic to an IP
> core that I have generate in EDK. I changed the vhdl file of an auto-
> generated IP core that is connected via FSL to the FPGA, but the
> behaviour of the program remains still the same. I've tried also to
> re-
> import the modified core to the project, but I still get errors due to
> the fact that the file xparameters.h doesn't contains the appropriated
> names.
> How can I do to let EDK notice changes in vhdl files?
> Thank you in advance!
> Giulio
>



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