FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 01-16-2004, 11:34 AM
Nicolas Matringe
Guest
 
Posts: n/a
Default Power-up input value detection

Hi
I am working on a design involving the cloning of an obsolete chip in an
FPGA (Altera EP10K family).
The behavior of the chip depends on some input values "at power-up" (no
mention of any reset there). My problem is to reliably detect power-up.

I could still manage something with the reset condition but that's not
exactly what the datasheet says ("If <input signal> is strapped Low at
power-up...")

--
____ _ __ ___
| _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
| | | | | (_| |_| | Invalid return address: remove the -
|_| |_|_|\__|\___/

Reply With Quote
  #2 (permalink)  
Old 01-16-2004, 05:29 PM
fabbl
Guest
 
Posts: n/a
Default Re: Power-up input value detection

How long are the "power-up values" stable? The EP10K has a stabilization
time that will need to be taken into account and compared against your old
part.


"Nicolas Matringe" <[email protected]> wrote in message
news:[email protected]
> Hi
> I am working on a design involving the cloning of an obsolete chip in an
> FPGA (Altera EP10K family).
> The behavior of the chip depends on some input values "at power-up" (no
> mention of any reset there). My problem is to reliably detect power-up.
>
> I could still manage something with the reset condition but that's not
> exactly what the datasheet says ("If <input signal> is strapped Low at
> power-up...")
>
> --
> ____ _ __ ___
> | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
> | | | | | (_| |_| | Invalid return address: remove the -
> |_| |_|_|\__|\___/
>



Reply With Quote
  #3 (permalink)  
Old 01-17-2004, 05:14 AM
Hal Murray
Guest
 
Posts: n/a
Default Re: Power-up input value detection

>I could still manage something with the reset condition but that's not
>exactly what the datasheet says ("If <input signal> is strapped Low at
>power-up...")


What do you think "at power-up" means?

Most chips I've worked with have a separate reset signal that
must be held active until the power is stable. "at power-up"
really means when reset goes away. It's the designer's
job to make sure that doesn't happen before power is stable.

Usually the signals you are looking at are not "strapped"
(or the problem would be simple) but there is a weak pullup/down
that is strong enough as long as no real driver is driving
that signal but doesn't add much load to mess up the normal
use of that pin. So the other half of the designer's job
is to make sure that nothing else drives those signals
until the chip has come out of reset.

Sometimes that last paragraph is wrong. If you are loading
the FPGA from a uProc, the uProc might have control of those
signals so the software has to get it right rather than using
pullups/downs.

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
IMPLEMENTING 32-BIT ALU WITH OVERFLOW DETECTION [email protected] Verilog 2 01-19-2007 01:23 AM
How is the input transition time used in calculating input delays ?? Rajat Mitra Verilog 2 10-13-2005 05:51 AM
RACE condition detection [email protected] Verilog 1 09-26-2005 06:26 AM
Edge Detection Ben Heard Verilog 2 09-12-2003 03:32 AM


All times are GMT +1. The time now is 01:47 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2021, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved