FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 06-12-2007, 06:33 AM
Guest
 
Posts: n/a
Default Power consumption problem

Hi,

when i implemented my architecture using ACTEL AFS600 (Fusion family)
i noticed that over 16MHz there is a gap in consumption, in fact when
i was changing my frequency from 1 kHz to 16 Mhz the power consumption
is varying from 13 mW till 20 mW when i reach 16 MHz there is a gap
and the power consumption jump directly to 30 mW,
anyone has any reason to explain this gap?

my speed grade is -2,


Regards,
A.

Reply With Quote
  #2 (permalink)  
Old 06-12-2007, 09:05 AM
Jim Granville
Guest
 
Posts: n/a
Default Re: Power consumption problem

[email protected] wrote:
> Hi,
>
> when i implemented my architecture using ACTEL AFS600 (Fusion family)
> i noticed that over 16MHz there is a gap in consumption, in fact when
> i was changing my frequency from 1 kHz to 16 Mhz the power consumption
> is varying from 13 mW till 20 mW when i reach 16 MHz there is a gap
> and the power consumption jump directly to 30 mW,
> anyone has any reason to explain this gap?
>
> my speed grade is -2,


Is it operating normally over that threshold ?
Normally, such a current discontinuity, also infers
an operational discontinuity.

Does the slope continue at just under 0.5mW/Mhz above that threshold ?

I'd test again with some simpler code, that you know has a very high Fmax.

-jg

Reply With Quote
  #3 (permalink)  
Old 06-12-2007, 09:28 PM
Guest
 
Posts: n/a
Default Re: Power consumption problem

On 12 juin, 04:05, Jim Granville <[email protected]>
wrote:
> [email protected] wrote:
> > Hi,

>
> > when i implemented my architecture using ACTEL AFS600 (Fusion family)
> > i noticed that over 16MHz there is a gap in consumption, in fact when
> > i was changing my frequency from 1 kHz to 16 Mhz the power consumption
> > is varying from 13 mW till 20 mW when i reach 16 MHz there is a gap
> > and the power consumption jump directly to 30 mW,
> > anyone has any reason to explain this gap?

>
> > my speed grade is -2,

>
> Is it operating normally over that threshold ?
> Normally, such a current discontinuity, also infers
> an operational discontinuity.
>
> Does the slope continue at just under 0.5mW/Mhz above that threshold ?
>
> I'd test again with some simpler code, that you know has a very high Fmax.
>
> -jg


that's the problem: the FPGA is still working good.
Yes the slope continue at just 0.5mW/Mhz above that threshold,
i tested the FPGA with other code and what s strange is that this
discontinuity still exist but for higher frequency (again the fpga is
still working good)

A.

Reply With Quote
  #4 (permalink)  
Old 06-13-2007, 12:02 AM
Jim Granville
Guest
 
Posts: n/a
Default Re: Power consumption problem

[email protected] wrote:
> On 12 juin, 04:05, Jim Granville <[email protected]>
> wrote:
>
>>[email protected] wrote:
>>
>>>Hi,

>>
>>>when i implemented my architecture using ACTEL AFS600 (Fusion family)
>>>i noticed that over 16MHz there is a gap in consumption, in fact when
>>>i was changing my frequency from 1 kHz to 16 Mhz the power consumption
>>>is varying from 13 mW till 20 mW when i reach 16 MHz there is a gap
>>>and the power consumption jump directly to 30 mW,
>>>anyone has any reason to explain this gap?

>>
>>>my speed grade is -2,

>>
>>Is it operating normally over that threshold ?
>>Normally, such a current discontinuity, also infers
>>an operational discontinuity.
>>
>>Does the slope continue at just under 0.5mW/Mhz above that threshold ?
>>
>>I'd test again with some simpler code, that you know has a very high Fmax.
>>
>>-jg

>
>
> that's the problem: the FPGA is still working good.
> Yes the slope continue at just 0.5mW/Mhz above that threshold,
> i tested the FPGA with other code and what s strange is that this
> discontinuity still exist but for higher frequency (again the fpga is
> still working good)


Yes, that does sound strange - what was the higher freq in the other test ?
16MHz should be 'low' by FPGA standards - were you using (or had
enabled?) any of the PLL/Clock multiplier resources ?

Did you ask Actel ? - those symptoms suggest they might not
be disabling everything they should, in the SW process ?

-jg

Reply With Quote
  #5 (permalink)  
Old 06-17-2007, 12:27 AM
Guest
 
Posts: n/a
Default Re: Power consumption problem

On 12 juin, 19:02, Jim Granville <[email protected]>
wrote:
> [email protected] wrote:
> > On 12 juin, 04:05, Jim Granville <[email protected]>
> > wrote:

>
> >>[email protected] wrote:

>
> >>>Hi,

>
> >>>when i implemented my architecture using ACTEL AFS600 (Fusion family)
> >>>i noticed that over 16MHz there is a gap in consumption, in fact when
> >>>i was changing my frequency from 1 kHz to 16 Mhz the power consumption
> >>>is varying from 13 mW till 20 mW when i reach 16 MHz there is a gap
> >>>and the power consumption jump directly to 30 mW,
> >>>anyone has any reason to explain this gap?

>
> >>>my speed grade is -2,

>
> >>Is it operating normally over that threshold ?
> >>Normally, such a current discontinuity, also infers
> >>an operational discontinuity.

>
> >>Does the slope continue at just under 0.5mW/Mhz above that threshold ?

>
> >>I'd test again with some simpler code, that you know has a very high Fmax.

>
> >>-jg

>
> > that's the problem: the FPGA is still working good.
> > Yes the slope continue at just 0.5mW/Mhz above that threshold,
> > i tested the FPGA with other code and what s strange is that this
> > discontinuity still exist but for higher frequency (again the fpga is
> > still working good)

>
> Yes, that does sound strange - what was the higher freq in the other test?
> 16MHz should be 'low' by FPGA standards - were you using (or had
> enabled?) any of the PLL/Clock multiplier resources ?
>
> Did you ask Actel ? - those symptoms suggest they might not
> be disabling everything they should, in the SW process ?
>
> -jg- Masquer le texte des messages précédents -
>
> - Afficher le texte des messages précédents -


the maximum frequency is 37 MHz, and no i m not using any PLL,
I asked atcel but i m still waiting for the answer!!!

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Over power consumption of APA1000.... What's the problem?? kypilop FPGA 0 11-10-2006 02:21 PM
Xilinx Spartan 3 DCI Power Consumption James Morrison FPGA 1 06-17-2005 01:14 PM
Virtex 4 Power consumption jason.stubbs FPGA 19 05-04-2005 04:32 PM
virtex2p power consumption praveen FPGA 1 09-26-2003 07:47 PM


All times are GMT +1. The time now is 09:48 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved