[email protected] wrote:
> Greetings,
>
> I have a situation where Post Translate timing is significantly
> different from behavioral/RTL simulation. I am not not speaking of
> simple delays, the outputs/data are different than what they should be.
>
>
> What is interesting is that the design works on the FPGA board.
> I implemented a serial port in loopback mode in Xilinx, if I type a
> character on Hyperterm I get the same returned from the FPGA.
>
> I have set timing constraints but to no effect.
>
> YZ
>
In a real design where correctness matters, I wouldn't discard
this discrepancy without taking a closer look...
It could mean that your design does't work at worst case timing,
or it could hide some unwelcome asynchronous feature or incorrect
clock domain crossing etc...
A couple of characters through Hyperterminal is not a good "proof"
of design correctness.
If you use Quartus, you could take a look at the Design Assistant's
report, or investigate the problem a bit further.
A potential error might create havoc much later.
Bert Cuzeau