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-   -   post translate and post PAR problems with XST and Modelsim (http://www.fpgacentral.com/group/showthread.php?t=62868)

[email protected] 09-14-2007 07:56 PM

post translate and post PAR problems with XST and Modelsim
 
I am trying to do a Virtex4 design, I have completed the post
synthesis (XST) simulations in Modelsim - everything appears fine.
When I run the PAR and simulate the generated model. I get all zeros
on the output. None of the registers in the desing appear to be
loading. I have specified the timing constraints for the period of the
clock (only that constraint). Is there something I may be forgetting
to do? My desing is runnig at 125Mhz.

Thanks


Gabor 09-17-2007 04:13 PM

Re: post translate and post PAR problems with XST and Modelsim
 
On Sep 14, 1:56 pm, [email protected] wrote:
> I am trying to do a Virtex4 design, I have completed the post
> synthesis (XST) simulations in Modelsim - everything appears fine.
> When I run the PAR and simulate the generated model. I get all zeros
> on the output. None of the registers in the desing appear to be
> loading. I have specified the timing constraints for the period of the
> clock (only that constraint). Is there something I may be forgetting
> to do? My desing is runnig at 125Mhz.
>
> Thanks



The post P&R simulation model contains a GSR (global set/reset)
signal which defaults to 100 nS assertion after power-on and
overrides all other logic set/reset functions. If your stimulation
relies on logic to be function before this 100 nS period is over,
you can have problems. If you don't want to change your stimulus
it is possible to driver the GSR signal yourself to reduce the
pulse width.

HTH,
Gabor



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