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Old 02-22-2012, 07:17 AM
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Default Post synthesis/NGD simulation

A demo vhdl project with IP stack DUT:

To go to Post synthesis/NGD simulation using VHDL net-list and GHDL free simulator : post ngd simulation VHDL .
To go to Post synthesis/NGD simulation using verilog net-list and icarus free simulator : post ngd simulation verilog .

h---://bknpk.no-ip.biz/my_web/IP_STACK/synt_ngd_1.html
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