FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 03-20-2005, 11:04 AM
Preben Holm
Guest
 
Posts: n/a
Default Post-map simulation models

Hi everyone...

Why is my statemachine not functioning the first many clock-cycles of
the post-map simulation?

Any explanation to that?



Thanks
Preben Holm
Reply With Quote
  #2 (permalink)  
Old 03-20-2005, 11:35 AM
Falk Brunner
Guest
 
Posts: n/a
Default Re: Post-map simulation models


"Preben Holm" <[email protected]> schrieb im Newsbeitrag
news:[email protected]
> Hi everyone...
>
> Why is my statemachine not functioning the first many clock-cycles of
> the post-map simulation?


Because global reset is active.

Regards
Falk



Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Post Synthesis and Post Place/Rout Simulation [email protected] Verilog 1 12-04-2007 11:59 PM
How to view internal signals in post synthesis simulation models (Xilinx ISE) thomasc Verilog 0 06-13-2005 03:18 AM
Post-Map Simulation Kavitha FPGA 1 06-27-2004 06:29 PM
VHDL simulation models from Alliance Semiconductors ALuPin FPGA 0 04-27-2004 11:47 AM


All times are GMT +1. The time now is 07:32 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved