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Old 10-17-2003, 09:23 PM
Swarna B
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Default Is it possible to define a preprocessor macro in Xilinx ISE

Is it possible to define a macro through the GUI of ISE or by any
command line
means? I mean, just like we give a +define+MACRO_NAME along with a
verilog
compilation commandline in Modelsim or in NC verilog. How do I do it?
As, otherwise, it becomes quite messy affair of commenting and
uncommenting
lines containing `define in the source code. Xilinx Answer records
don't seem to have anything on this.

Regrds
Swarna
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