FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 10-31-2007, 12:19 PM
Pablo
Guest
 
Posts: n/a
Default Is it possible to debug a vhdl design over jtag?

Hi,

I would like to debug a vhdl design over Jtag. Is it possible?. As
XMD for EDK but for vhdl code.

My best regards
Pablo

Reply With Quote
  #2 (permalink)  
Old 10-31-2007, 12:23 PM
Antti
Guest
 
Posts: n/a
Default Re: Is it possible to debug a vhdl design over jtag?

On 31 Okt., 12:19, Pablo <[email protected]> wrote:
> Hi,
>
> I would like to debug a vhdl design over Jtag. Is it possible?. As
> XMD for EDK but for vhdl code.
>
> My best regards
> Pablo


yes

Reply With Quote
  #3 (permalink)  
Old 10-31-2007, 12:27 PM
comp.arch.fpga
Guest
 
Posts: n/a
Default Re: Is it possible to debug a vhdl design over jtag?

On 31 Okt., 12:19, Pablo <[email protected]> wrote:
> Hi,
>
> I would like to debug a vhdl design over Jtag. Is it possible?. As
> XMD for EDK but for vhdl code.
>
> My best regards
> Pablo


check out "ChipScope Pro"

Reply With Quote
  #4 (permalink)  
Old 10-31-2007, 01:29 PM
morphiend
Guest
 
Posts: n/a
Default Re: Is it possible to debug a vhdl design over jtag?

On Oct 31, 7:27 am, "comp.arch.fpga" <[email protected]> wrote:
> On 31 Okt., 12:19, Pablo <[email protected]> wrote:
>
> > Hi,

>
> > I would like to debug a vhdl design over Jtag. Is it possible?. As
> > XMD for EDK but for vhdl code.

>
> > My best regards
> > Pablo

>
> check out "ChipScope Pro"


ChipScope is an awesome way to get "eyes" into the operation of the
internals of your circuitry. It does not provide the capability to
"debug" like software where you can tweak registers, memory, PC, etc
on the fly. It has been a savior many times when trying to figure out
why something that should have happened, but didn't.

Tricks of the trade with using CS include:
1) Make sure you have MORE than what you want brought out in the
triggers. Rebuilding larger systems can take a long time.
2) Make sure you have MORE than what you initially think you need in
the data collection. Same reason as above.
3) Basic w/ Edges is a god-send and should be the default setting for
data.
4) There is a hard limit on the amount of data/trigger signal you can
have per ILA (256, maybe 512). If you need more, you can more ILA's,
but its best to try to limit the signals you need to fit into an ILA.
If what you need to see won't fit, then maybe you need to re-think
exactly what you need.
5) ChipScope can be used together w/ XMD. This can allow you the
ability to inject certain conditions without having to run large
software programs to probe hardware.

Reply With Quote
  #5 (permalink)  
Old 10-31-2007, 02:30 PM
Andy
Guest
 
Posts: n/a
Default Re: Is it possible to debug a vhdl design over jtag?

On Oct 31, 7:29 am, morphiend <[email protected]> wrote:
> On Oct 31, 7:27 am, "comp.arch.fpga" <[email protected]> wrote:
>
> > On 31 Okt., 12:19, Pablo <[email protected]> wrote:

>
> > > Hi,

>
> > > I would like to debug a vhdl design over Jtag. Is it possible?. As
> > > XMD for EDK but for vhdl code.

>
> > > My best regards
> > > Pablo

>
> > check out "ChipScope Pro"

>
> ChipScope is an awesome way to get "eyes" into the operation of the
> internals of your circuitry. It does not provide the capability to
> "debug" like software where you can tweak registers, memory, PC, etc
> on the fly. It has been a savior many times when trying to figure out
> why something that should have happened, but didn't.
>
> Tricks of the trade with using CS include:
> 1) Make sure you have MORE than what you want brought out in the
> triggers. Rebuilding larger systems can take a long time.
> 2) Make sure you have MORE than what you initially think you need in
> the data collection. Same reason as above.
> 3) Basic w/ Edges is a god-send and should be the default setting for
> data.
> 4) There is a hard limit on the amount of data/trigger signal you can
> have per ILA (256, maybe 512). If you need more, you can more ILA's,
> but its best to try to limit the signals you need to fit into an ILA.
> If what you need to see won't fit, then maybe you need to re-think
> exactly what you need.
> 5) ChipScope can be used together w/ XMD. This can allow you the
> ability to inject certain conditions without having to run large
> software programs to probe hardware.


Synplicty's Verify product merges the capabilities of Xilinx chipscope
with a "source level debugger" operating with your vhdl/verilog.
"source level debugger" is a generous title, but it is the closest to
the real thing available.

Andy

Reply With Quote
  #6 (permalink)  
Old 10-31-2007, 05:05 PM
MM
Guest
 
Posts: n/a
Default Re: Is it possible to debug a vhdl design over jtag?

"Pablo" <[email protected]> wrote in message
news:[email protected] ps.com...
> Hi,
>
> I would like to debug a vhdl design over Jtag. Is it possible?. As
> XMD for EDK but for vhdl code.
>


For the purpose of this discussion VHDL is a language describing hardware.
Every change in code requires new hardware to be synthesized. For this
simple reason software style debugging is not really possible with real
hardware. However, you can debug all you want (before going to hardware)
with VHDL simulators such as, for example, Modelsim, or Active HDL.


/Mikhail


Reply With Quote
  #7 (permalink)  
Old 10-31-2007, 08:30 PM
Mike Treseler
Guest
 
Posts: n/a
Default Re: Is it possible to debug a vhdl design over jtag?

MM wrote:

> For the purpose of this discussion VHDL is a language describing hardware.
> Every change in code requires new hardware to be synthesized. For this
> simple reason software style debugging is not really possible with real
> hardware. However, you can debug all you want (before going to hardware)
> with VHDL simulators such as, for example, Modelsim, or Active HDL.


Good point.
Some prefer working out the logical problems
in a tight loop at the code level on a simulator.
This avoids waiting for a special place and route
on each try.

-- Mike Treseler
Reply With Quote
  #8 (permalink)  
Old 11-06-2007, 08:26 AM
Pablo
Guest
 
Posts: n/a
Default Re: Is it possible to debug a vhdl design over jtag?

Thanks for your advices. I suppose that Chipscope is a good option.




Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
VHDL Design Pattern Book Erik Anderson FPGA 1 09-12-2007 02:59 PM
TCL SCRIPT AND VHDL DESIGN AAA FPGA 2 01-04-2006 05:50 AM
openrisc, jp1 jtag debug utility jeff murphy FPGA 4 09-07-2005 01:56 AM
Altera nios-debug via JTAG evan FPGA 0 08-29-2005 06:53 AM
PCI design with vhdl kender FPGA 3 12-11-2004 04:06 PM


All times are GMT +1. The time now is 06:25 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved