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  #1 (permalink)  
Old 10-29-2007, 05:10 PM
Wei Wang
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Default Is it possible to check how cache memories are mapped to FPGA block rams?

Hello, I implemented an ARM1176JZFS on a Virtex 5 FPGA, but it seems
that the
cache memories of the processor are not behaving correctly and I
have to turn off the caches for application programs
to run correctly on the processor. Just wondering whether it is
possible to check whether the processor memories have been mapped
correctly onto the block rams on FPGA. Thanks, -Wei

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  #2 (permalink)  
Old 10-29-2007, 05:17 PM
Antti
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Default Re: Is it possible to check how cache memories are mapped to FPGA block rams?

On 29 Okt., 17:10, Wei Wang <[email protected]> wrote:
> Hello, I implemented an ARM1176JZFS on a Virtex 5 FPGA, but it seems
> that the
> cache memories of the processor are not behaving correctly and I
> have to turn off the caches for application programs
> to run correctly on the processor. Just wondering whether it is
> possible to check whether the processor memories have been mapped
> correctly onto the block rams on FPGA. Thanks, -Wei


depends on the definition of "correct"
you can use FPGA editor to see the mapping to device primitives if you
wish
but that want tell you why your design is not working

Antti

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  #3 (permalink)  
Old 10-29-2007, 08:42 PM
Eric Smith
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Default Re: Is it possible to check how cache memories are mapped to FPGA block rams?

Wei Wang <[email protected]> writes:
> Hello, I implemented an ARM1176JZFS on a Virtex 5 FPGA, but it seems
> that the
> cache memories of the processor are not behaving correctly and I
> have to turn off the caches for application programs
> to run correctly on the processor. Just wondering whether it is
> possible to check whether the processor memories have been mapped
> correctly onto the block rams on FPGA. Thanks, -Wei


Perhaps if you post the actual project (or put a copy on a web site and
post a URL), some of us can take a look at it and try to help debug
it. Otherwise we don't have very much to go on.

Eric
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  #4 (permalink)  
Old 10-30-2007, 11:16 AM
Wei Wang
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Default Re: Is it possible to check how cache memories are mapped to FPGA block rams?

On Oct 29, 7:42 pm, Eric Smith <[email protected]> wrote:
> Wei Wang <[email protected]> writes:
> > Hello, I implemented an ARM1176JZFS on a Virtex 5 FPGA, but it seems
> > that the
> > cache memories of the processor are not behaving correctly and I
> > have to turn off the caches for application programs
> > to run correctly on the processor. Just wondering whether it is
> > possible to check whether the processor memories have been mapped
> > correctly onto the block rams on FPGA. Thanks, -Wei

>
> Perhaps if you post the actual project (or put a copy on a web site and
> post a URL), some of us can take a look at it and try to help debug
> it. Otherwise we don't have very much to go on.
>
> Eric


Eric, I appreciate your willingness to dig further to help, but my
question was how I could check the block ram mapping of my design
which I thought it was quite generic, and I would expect answers, such
as, look at somewhere or look for something in the synthesis log file,
or open fpga editor and look for instantiations of primitives. BTW, I
suppose most of us in this group do not work for ourselves, only lazy
university students would post their entire project and let somebody
else do the work for them. Thanks!

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  #5 (permalink)  
Old 10-30-2007, 01:18 PM
morphiend
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Default Re: Is it possible to check how cache memories are mapped to FPGA block rams?

On Oct 30, 6:16 am, Wei Wang wrote:
> On Oct 29, 7:42 pm, Eric Smith wrote:
> > Perhaps if you post the actual project (or put a copy on a web site and
> > post a URL), some of us can take a look at it and try to help debug
> > it. Otherwise we don't have very much to go on.

>
> > Eric

>

<SNIP>
> BTW, I suppose most of us in this group do not work for ourselves, only lazy
> university students would post their entire project and let somebody
> else do the work for them. Thanks!


Now, now. Don't be too hasty. That's what we do with Xilinx all the
time when their software tools don't work "just right" or you hit that
invisible brick wall that only someone with eyes from inside the brick
wall can tell you why the wall exists (read: Webcases).

So long as what you're working on is not proprietary, the nature of
"open source" mindedness is to share with others and gather feedback.
That's what posting your MHS file would provide.

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  #6 (permalink)  
Old 10-30-2007, 01:46 PM
HT-Lab
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Default Re: Is it possible to check how cache memories are mapped to FPGA block rams?


"Eric Smith" <[email protected]> wrote in message
news:[email protected]
> Wei Wang <[email protected]> writes:
>> Hello, I implemented an ARM1176JZFS on a Virtex 5 FPGA, but it seems
>> that the
>> cache memories of the processor are not behaving correctly and I
>> have to turn off the caches for application programs
>> to run correctly on the processor. Just wondering whether it is
>> possible to check whether the processor memories have been mapped
>> correctly onto the block rams on FPGA. Thanks, -Wei

>
> Perhaps if you post the actual project (or put a copy on a web site and
> post a URL), some of us can take a look at it and try to help debug
> it. Otherwise we don't have very much to go on.
>
> Eric


I am not sure that putting his expensive ARM1176 core on the web would be
appreciated by ARM :-)

Did you write this core yourself? if not then I am sure you can get some
excellent support from ARM to fix this issue,

Hans
www.ht-lab.com



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  #7 (permalink)  
Old 10-30-2007, 10:22 PM
Eric Smith
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Default Re: Is it possible to check how cache memories are mapped to FPGA block rams?

Wei Wang wrote:
> Eric, I appreciate your willingness to dig further to help, but my
> question was how I could check the block ram mapping of my design
> which I thought it was quite generic, and I would expect answers, such


Without looking at your HDL code, I don't think we have any clue how
you've attached the blockrams to your CPU, so I'm not sure how we
could tell you how to check the mapping.

> BTW, I
> suppose most of us in this group do not work for ourselves, only lazy
> university students would post their entire project and let somebody
> else do the work for them.


In general, I agree. But sometimes it's hard to offer any help without
more detail, and sometimes the easiest way to see the relevant detail
is to look at the HDL.

I'm sorry that I don't have any more specific advice to offer.

Best regards,
Eric

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  #8 (permalink)  
Old 10-31-2007, 02:35 PM
Mike Lewis
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Default Re: Is it possible to check how cache memories are mapped to FPGA block rams?

Wei,

I have worked with an ARM926 soft core. This deliverable provided an
implementation guide as well as a simulation environment to verify the RAM
integration. I would have thought the ARM11 would have a similar thing.

Whether it is FPGA or ASIC the RAM integration follows the same process. The
RTL simulation environment will ensure you have correctly connected the
memories.

Mike


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