On 2006-12-11,
[email protected] <
[email protected]> wrote:
> vits wrote:
>
>> ok I will put it like this..
>> always @(*)
>> begin
>> a=b;
>> @(posedge clk);
>> c=a;
>> end
>> What does it mean.
>
> It is a bad idea. Synthesis tools will reject this code, and although a
> simulator will process it, nobody reading your code will be able to
> understand or maintain it.
>
> To help you understand it, I'll explain what it does in simulation...
>
> 1) It waits for an event on a, b or clk
> 2) It sets a=b
> 3) It waits for a rising clock edge
> 4) It sets c=a
> 5) It loops from step 1.
I thought this was an intriguing question because I did not know how
@(*) deals with clk in the case above so I looked it up in
the Verilog standard. (IEEE Std 1364-2005 to be exact, section
9.7.5.)
It turns out that @(*) should add all (net and variable) identifiers to
the sensitivity list unless at least one of the following is true:
* It is only used as a destination for an assignment
* It only appears in a wait or event expression.
The following is an example from the standard:
always @* begin // equivalent to a(b)
@(i) kid = b; // i is not added to @*
end
So the example above should be modified as follows:
1) It waits for an event on a or b
I could also note that the version of Modelsim I'm using (6.2b) does seem
to add identifiers in event expressions to the sensitivity list
unfortunately.
/Andreas