FPGA Central

There is a fairly well written article on crossing clock domains
that has been published this week. The online version is at:

http://www.chipdesignmag.com/display...d=32&issueId=5

There is a minor problem with the figure numbers in the text (off by one)
but it is pretty obvious.

Philip



===================
Philip Freidin
[email protected]
Host for WWW.FPGA-FAQ.COM

Hi Philip,
Thanks for the link! As you say, a pretty good article.
There's one little thing I'd like to say! I prefer the circuit Rick
presented here on CAF over the one presented in fig.3. Search Google Groups
for subject "Async logic in FPGAs" in comp.arch.fpga . Rick's circuit works
well even if the signal to be synchronised can clock faster than the
synchronising clock. Of course, some of the faster clock's transitions can
still be missed, but any burst of, for example, two fast clocks on the input
signal will (almost*) always be caught by at least one clock enable in the
synchronised domain.
A practical example of this is debouncing a switch input with a slow clock.
Imagine a key switch input being sampled at 1kHz. The circuit in Fig.3 could
miss the key press if the bouncy signal has an even number of rising edges.
Rick's circuit gets the bugger (almost*) everytime!
Cheers, Syms.

* Metastability is always possible, no matter how remote that possibility.
In the 1kHz example the synchronising circuit could stay metastable for 1ms!

"Philip Freidin" <[email protected]> wrote in message
news:[email protected]
> There is a fairly well written article on crossing clock domains
> that has been published this week. The online version is at:
>
> http://www.chipdesignmag.com/display...d=32&issueId=5
>
> There is a minor problem with the figure numbers in the text (off by one)
> but it is pretty obvious.
>
> Philip

Hi Symon,

On Mon, 2 Aug 2004 14:15:01 -0700, "Symon" <[email protected]> wrote:
>Hi Philip,
>Thanks for the link! As you say, a pretty good article.
>There's one little thing I'd like to say! I prefer the circuit Rick
>presented here on CAF over the one presented in fig.3. Search Google Groups
>for subject "Async logic in FPGAs" in comp.arch.fpga .

Or in the archive at www.FPGA-FAQ.com article 59400.

>Rick's circuit works
>well even if the signal to be synchronised can clock faster than the
>synchronising clock. Of course, some of the faster clock's transitions can
>still be missed, but any burst of, for example, two fast clocks on the input
>signal will (almost*) always be caught by at least one clock enable in the
>synchronised domain.

I agree, Rick's design is a better way to pass the flag than Roy's figure 3.

>A practical example of this is debouncing a switch input with a slow clock.
>Imagine a key switch input being sampled at 1kHz. The circuit in Fig.3 could
>miss the key press if the bouncy signal has an even number of rising edges.
>Rick's circuit gets the bugger (almost*) everytime!
>Cheers, Syms.
>
>* Metastability is always possible, no matter how remote that possibility.
>In the 1kHz example the synchronising circuit could stay metastable for 1ms!

I have added links to both of these articles, and also some articles by
Peter Alfke at the end of the FAQ page on metastables at

http://www.fpga-faq.com/FAQ_Pages/00...etastables.htm

Thanks again for the ref to a good article,

Philip



===================
Philip Freidin
[email protected]
Host for WWW.FPGA-FAQ.COM

No worries, Philip. I'm just relieved we seem to have got away with
mentioning the 'M' word without getting a 200 post thread! I reckon your
excellent FAQ with the articles from yourself and various distinguished
contributors is doing its job!
Cheers, Syms.
"Philip Freidin" <[email protected]> wrote in message
news:[email protected]
>
> Thanks again for the ref to a good article,
>
> Philip