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Old 05-31-2006, 12:56 AM
Joseph
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Default PLB transfers: PPC to IP

I have a piece of IP that acts as a slave on the PLB. I would like
writes to this IP to be 64bits, while reads from it are OK at 32bits.
The sample driver that was generated by the IP wizard gives functions
for reads/writes or 32 bits as expected (by mapping them to
XIo_In/Out32). Do I need to do writes in two transfers? If not, how
do I write 64bits? I've looked over the PPC 405 Block Reference Guide
and it seems that it should be possible to read/write 64 bits all at
once just by virtue of having that wide of a bus coming in and out of
the block. The cacheline transfers are discussed in that document as
possibly being doublewords. I am a bit confused by all of this (if that
wasn't clear already). I would probably be able to find my answer
after a good deal of time/pain, but hopefully someone out there can
clarify things a little for me. Just knowing if it was possible or not
for a user program to do the 64bit write would help me move forward.

I'd appreciate any clarification and/or pointers to relevant
documentation. I can provide more info about my design or my confusion
if it is useful.

Thanks in advance,
Joey

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Old 05-31-2006, 10:09 AM
Ben Jones
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Default Re: PLB transfers: PPC to IP

Hi Joey,

"Joseph" <[email protected]> wrote in message
news:[email protected] ups.com...
> I have a piece of IP that acts as a slave on the PLB. I would like
> writes to this IP to be 64bits, while reads from it are OK at 32bits.
> The sample driver that was generated by the IP wizard gives functions
> for reads/writes or 32 bits as expected (by mapping them to
> XIo_In/Out32). Do I need to do writes in two transfers? If not, how
> do I write 64bits?


The fundamental limitation here is that the PowerPC-405 is a 32-bit core. So
there are no instructions to load/store 64 bits of data at a time as an
atomic unit. So from the processor core's perspective, you have to do two
32-bit stores. (The XIo_In and XIo_Out functions are basically just a
wrapper around load/store instructions, but with an added "eieio" to make
sure the operations don't get re-ordered by the hardware.)

As you say, the PLB is in fact capable of doing multi-word transfers, and is
wide enough to do 64-bit transfers in a single data beat. However, aside
from enabling this functionality in the first place, the processor has no
control over whether this actually occurs.

Without having done any experiments, my gut feeling is that using two calls
to XIo_Out() back to back will not result in a 64-bit transfer, because of
these "eieio"s. Your best bet is probably to try something like:

typedef unsigned long long bits64;
volatile bits64 *my_reg = (volatile bits64 *)(REG_ADDRESS);

*my_reg = some_value;

....and then watch the bus and see what happens.

Hope that helps, or least makes sense...

-Ben-


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