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Old 04-26-2006, 05:59 PM
Fizzy
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Default PLB

I want to verify few of my concepts about Processor Local Bus
(CoreConnect) in Xilinx FPGA. I know each master on PLB is connected to
PLB arbiter on a seperate read and write bus. But i am confused about
the shared connection between the PLB slave and PLB arbiter. Is this
connection is parallel too. I mean i can see its shared but shared
means still 64-bit parallel right ????

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