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Old 10-27-2003, 12:15 AM
Pablo Bleyer Kocik
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Default Picky WebPACK 6.1

Hello.

I am designing a memory interface for an MCU in a SpartanII with Webpack
6.1.02i. To optimize pin usage in my design, address and data buses are
muxed and I am trying to use latched addresses.

To synthetize my latch under Verilog, I first wrote.

always @(AD, A_g) if (A_g) A_r <= AD;

where AD is the address/data vector input of type reg[7:0], A_g is the gate
signal and A_r the internal address latch. According to the Libraries Guide,
multiple transparent data latches are implemented as macros in the SpartanII
and the synthesis step reports me and 8-bit latch being generated with the
same Verilog syntax suggested by this guide. However, translate gives
warnings and mapping fails:

[...]
Checking expanded design ...
WARNING:NgdBuild:477 - clock net 'A_g_BUFGP' has non-clock connections.
These
problematic connections include:
pin I1 on block I2_EnableTr_INV1 with type LUT3
[...]
Started process "Map".

Using target part "2s100tq144-5".
ERROR:MapLib:93 - Illegal LOC on IPAD symbol "A_g" or BUFGP symbol
"A_g_BUFGP"
(output signal=A_g_BUFGP), IPAD-IBUFG should only be LOCed to GCLKIOB
site.

Now, I look into the Libraries Guide again and I see that latches with
inverted gates are primitives in the SpartanII. I change my equations a
little:

wire nA_g = !A_g;
always @(AD, nA_g) if (!nA_g) A_r <= AD;

And, voilą, this time it works. Synthesis reports also an 8-bit latch being
detected.

Why is Webpack being so picky? I was expecting that it should have detected
automatically the inverted gate signal and generated the correct signal for
its primitive itself...

Also, I have being trying unsuccessfully to get it to recognize and infer
block rams correctly for memory arrays, following the Verilog syntax
suggested by the Xilinx synthesis guide, but most of the time it generates
distributed RAMs...

Regards.


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