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Old 10-26-2005, 12:54 PM
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Default Physical interface for PCI express(PIPE) electrical information

Hi All,


i request somebody who worked on or having knowledge about Physical
interface for PCI express(PIPE) to reply for my below query.


i am trying to understand the PIPE interface for my application. INTEL
has no where specified the electrical interface of the PIPE if we use
the PHY as an external component and PCI express link layer in FPGA.
when i spend hours together to find this, finally i got one device from
PHILIPS PX1011a which supports SSTL2 standard.


is there any standard electrical interface defined for this kind of
application? if it is, can anybody can share the link to those
documents to me.


thanks in advance


S.RANGA REDDY

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Old 10-28-2005, 09:35 PM
PeteS
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Default Re: Physical interface for PCI express(PIPE) electrical information

The PCI Express physical layer interface is a fully defined standard,
and part of the larger standard.
It matters not at all what your application is. Go here:

http://www.pcisig.com/specifications/pciexpress/

Get the spec

Read it

Interestingly, you stated you had found a device with the SSTL2 spec -
that's memory

Cheers

PeteS

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Old 10-28-2005, 09:38 PM
PeteS
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Default Re: Physical interface for PCI express(PIPE) electrical information

Reading your query again, it seems you are trying to interface to an
Intel device (communications controller perhaps).

1. Intel does not own the PCI Express spec (although they probably paid
more than anyone else to getting it made).

2. Intel devices that claim to meet a specification generally do.
(There are exceptions, but even that is noted in the data sheet).

3. You seem confused about what you are trying to do

Cheers

PeteS

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Old 10-29-2005, 06:46 PM
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Default Re: Physical interface for PCI express(PIPE) electrical information

The answer to your question is NO.

The PIPE specification is not part of the PCI Express Base
Specification. It is not even governed by the PCI-SIG. It is a
"suggestion" from Intel for a logical interface between the MAC and the
PHY, in the physical layer of a PCI Express component. I think the
idea is to suggest that people designing PHY functions use a common
interface, to foster portability between PHY vendors/implementations.

As you note, it describes the logical behavior of such an interface and
doesn't discuss anything else. At the time it was written, I don't
think they were even contemplating external PHY devices like the
Philips PX1011a. However, you can imagine that someone wanting to do
an external PHY would probably take the PIPE specification as a
reasonable starting point for their interface behavior. What
electricals to use? Whatever you want, as long as it works and you
think your potential customers will be satisfied. Philips used SSTL2,
as you point out, which seems to work well with, say, a Spartan3 FPGA
from Xilinx.

So, then, if you are using an external PHY, you need to evaluate your
options and then select one -- and design to the specifications in the
vendor's data sheet.

Eric Crabill
Xilinx, Incorporated

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