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Old 05-17-2004, 11:11 AM
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Default Phase alignment


I have the following problem:

My FPGA has an input clock CLOCK30. This clock comes from an external

The clock CLOCK30 is used as the input clock of a PLL which
generates a fast clock CLOCK90 whose period is a third (90MHz).

For my FPGA controller I need CLOCK90 to be in phase alignment with

CLOCK30 is also used to clock the data into the external transceiver.
(clock name at FPGA output pin (CLOCK30_OUT)

So how can I manage that CLOCK30_OUT is in phase alignment with
CLOCK30 and

I am using Altera Cyclone Device with its PLL.

The paper "AN251 : Using PLLs in Cyclone Devices" does not show
about aligning phase relationship of clock input pin, clock at
register clock port AND clock output pin"

I would appreciate your help.

Kind regards
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