FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 11-07-2003, 07:46 PM
Muthu
Guest
 
Posts: n/a
Default PCI - X Boot up

Hi,

I am having PCIX Core in FPGA. Hence after power on reset, it takes
some time (FPGA configuration) to get the PCI-X Core logic. Lets say
it is 2 seconds for example.

after this time only, logics being realised and it can respond to PCI
configuration Cycles.

My question is, after power ON when the PCIX controller starts its
enumaration process. ie., reading configuration space

Thanks in advance.

Regards,
Muthu
Reply With Quote
  #2 (permalink)  
Old 11-07-2003, 10:10 PM
Eric Crabill
Guest
 
Posts: n/a
Default Re: PCI - X Boot up


Hello,

Once the power becomes "good" there is a minimum 100 ms delay
before the RST# signal deasserts.

Unless you are designing a 32-bit PCI card, you MUST have the
FPGA finished with bitstream loading before RST# deasserts.
This applies to any compliant PCI-X design regardless of bus
width, and also to any PCI design that is 64-bits wide.

The reason for this is that your FPGA design MUST be loaded
so that it can detect the busmode initialization pattern,
which is broadcast at the deassertion of RST#. If you miss
this, you are in big trouble...

Once RST# is deasserted, you then have 2^25 or 2^27 cycles,
depending on the bus frequency, until the first configuration
access to your device.

Eric
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
MicroBlaze : can I assign Boot BRAM address other than 0x0? louis lin FPGA 0 10-29-2003 10:53 AM
PPC boot ram FPGA 0 10-22-2003 04:16 PM


All times are GMT +1. The time now is 01:49 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved