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Old 06-03-2004, 12:07 PM
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Default Partial Reconfiguration clock enable problem


I have finished a Xilinx partial reconfiguration design which runs
succesfully on my Virtex II Pro. Yet, there is one line of a
reconfigurable module which crosses the module boundary. It is the
constant clock enable signal for a reconfiguration module which not me
but the tool added. This constant is generated in a LUT within the
boundaries of another module, yet only connected to a LUT within the
correct module (no further connections).
I would be happy to know how to remove this boundary corssing signal.
Did anybody encounter similar problems or may help me with some hints?

Thanks a lot,

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