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Old 09-13-2007, 10:04 AM
Dolphin
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Default overloading ' operators in VHDL

Hello,

I know that it is possible to overload operators like 'and', 'or',
'+',... by using a function with the name "and", "or", "+",... .
Is it also possible to overload the attribute operators like: 'high,
'left, 'low, ..? Is it possible to create your own attributes?

best regards,
Karel

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Old 09-14-2007, 04:32 AM
Mark McDougall
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Default Re: overloading ' operators in VHDL

Dolphin wrote:

> I know that it is possible to overload operators like 'and', 'or',
> '+',... by using a function with the name "and", "or", "+",... .
> Is it also possible to overload the attribute operators like: 'high,
> 'left, 'low, ..? Is it possible to create your own attributes?


I doubt it - I don't think the ' is an operator as such..

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
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Old 09-17-2007, 05:20 PM
RCIngham
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Default Re: overloading ' operators in VHDL

>Is it also possible to overload the attribute operators like: 'high,
>'left, 'low, ..? Is it possible to create your own attributes?
>

Yes, it is possible to create new ones and possibly to overload existin
ones, but probably not worth it. The attributes are added to the databas
and used by software tools that process it, for instance physica
implementation tools. Various of these come with a set of tool-specifi
attributes that you can use as directives. Not sure whether simulator
will do useful things with user-defined attributes...


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