FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 04-20-2006, 12:53 PM
Dolphin
Guest
 
Posts: n/a
Default OPB_SPI timing problems


Hello,

I have a microblaze system containing an OPB_SPI core.
It used to work without adding special timing constraints for this core
It seems that I have a timing problem now that my FPGA is getting full
The data coming from the SPI core is now shifted by one bit. I hav
noticed that the SPI_OPB uses a seperate clock, constraining this cloc
used to help but I think that I should add more constraints.

Has anybody had a similar problem? The xilinx site gives no info on th
required timing constraints for this core.

thanks and best regards,
Karel D
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Problems with Timing Simulation [email protected] FPGA 6 07-08-2005 09:04 AM
Connecting ADC to Opb_Spi core Marco FPGA 7 07-05-2005 09:07 PM
why can't i use opb_spi core in EDK6.3? ARRON FPGA 5 06-02-2005 10:38 AM
Problems in timing simulations michel leconte FPGA 4 01-18-2005 07:10 PM
Problems in timing simulations michel leconte FPGA 1 01-18-2005 09:48 AM


All times are GMT +1. The time now is 05:39 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved