FPGA Central

Hello

I'm planning to do a microblaze design using external DDR memory using the opb_ddr
core. However I'd like to know if there is any constraints on how to connect
(which banks/pins ...) the DDR chip. Here I only have 1 point to point connection
of a 16 bits wide DDR.

I was planning on using two banks for all the DQS/DQM/DQ then another bank for the
control & address signals.

I haven't seen much info about that in the opb_ddr doc. But on DDR interface appnotes,
some have specific constrainst so I prefer to ask before making the board


Sylvain

Sylvain Munaut wrote:
> Hello
>
> I'm planning to do a microblaze design using external DDR memory using
> the opb_ddr
> core. However I'd like to know if there is any constraints on how to
> connect
> (which banks/pins ...) the DDR chip. Here I only have 1 point to point
> connection
> of a 16 bits wide DDR.
>
> I was planning on using two banks for all the DQS/DQM/DQ then another
> bank for the
> control & address signals.
>
> I haven't seen much info about that in the opb_ddr doc. But on DDR
> interface appnotes,
> some have specific constrainst so I prefer to ask before making the
> board
There's several things to consider: First, you can't put DQS signals and
DQ-signals in the same IO-tiles, because they use different clocks and
there can only be one clock per tile for the IO-registers. That's one
thing I stumbled upon in the past...

Second, the plb_ddr-controller from EDK3.2 (don't know if this applies
to the opb_ddr in EDK6.X) suggested a clock feedback path, i.e. a
separate trace feeding the clock sent to the DDR back into the FPGA.
They use that to determine how to compensate for PCB routing delays. If
you don't have that, you'll probably have to waste a DCM and do some
fiddling around to figure out the correct phase shifts and such.

Third, remember that DDR-SDRAM has a MINIMAL clock rate at which it can
operate. With the myriad of different manufacturers, types and
speedgrades of SDRAM-chps available you should look out not to
accidentally get a chip that doesn't run as "slow" as your controller.

If you're planning to use high clock rates, Xilinx recommends you use
local clocks for the DQS signals, and then you'd have to use specific
pins for the corresponding data signals. In Xilinx' Memory Corner you
can download a "Memory Interface Generator" that can help with the pin
assignments.

Other than that, the DDR-chip probably uses SSTL2, which means you have
to hook up all the Vref-pins to 1,25V, so they are not available to use
as I/Os. Termination is an issue as well, so you should connect the
VRN/VRP-pins as well to be able to use the DCIs for termination.
Depending on the board layout it might be neccessary to use series
resistors and/or pullups at the DDR chip as well.

cu,
Sean

Sean Durkin wrote:
> Sylvain Munaut wrote:
> > Hello
> >
> > I'm planning to do a microblaze design using external DDR memory
using
> > the opb_ddr
> > core. However I'd like to know if there is any constraints on how
to
> > connect
> > (which banks/pins ...) the DDR chip. Here I only have 1 point to
point
> > connection
> > of a 16 bits wide DDR.
> >
> > I was planning on using two banks for all the DQS/DQM/DQ then
another
> > bank for the
> > control & address signals.
> >
> > I haven't seen much info about that in the opb_ddr doc. But on DDR
> > interface appnotes,
> > some have specific constrainst so I prefer to ask before making the

> > board
> There's several things to consider: First, you can't put DQS signals
and
> DQ-signals in the same IO-tiles, because they use different clocks
and
> there can only be one clock per tile for the IO-registers. That's one

> thing I stumbled upon in the past...
>
> Second, the plb_ddr-controller from EDK3.2 (don't know if this
applies
> to the opb_ddr in EDK6.X) suggested a clock feedback path, i.e. a
> separate trace feeding the clock sent to the DDR back into the FPGA.
> They use that to determine how to compensate for PCB routing delays.
If
> you don't have that, you'll probably have to waste a DCM and do some
> fiddling around to figure out the correct phase shifts and such.
>

I got burned on this, too. I have a SO-DIMM design with "59-bit" wide
data interface because of IOB assignments. The IOB tiles have the same
pairing as differential signals, so it's easy to find them in the pin-
out diagrams.

> Third, remember that DDR-SDRAM has a MINIMAL clock rate at which it
can
> operate. With the myriad of different manufacturers, types and
> speedgrades of SDRAM-chps available you should look out not to
> accidentally get a chip that doesn't run as "slow" as your
controller.
>

This is less likely to bite you if you bothered to use DDR in the first
place. Minimum for some chips is 83 MHz, others 66 MHz for DDR 1.

> If you're planning to use high clock rates, Xilinx recommends you use

> local clocks for the DQS signals, and then you'd have to use specific

> pins for the corresponding data signals. In Xilinx' Memory Corner you

> can download a "Memory Interface Generator" that can help with the
pin
> assignments.
>
> Other than that, the DDR-chip probably uses SSTL2, which means you
have
> to hook up all the Vref-pins to 1,25V, so they are not available to
use
> as I/Os. Termination is an issue as well, so you should connect the
> VRN/VRP-pins as well to be able to use the DCIs for termination.
> Depending on the board layout it might be neccessary to use series
> resistors and/or pullups at the DDR chip as well.
>

Probably not an issue with one 16-bit part, but with a large data bus
DCI will probably increase your power to an unacceptable level if you
don't have adequate heatsinking. I've burned up some FG456 package
devices this way (64 data bits of DCI adds about 4W by my estimate).

For chips glued to the board (not DIMM or SO-DIMM) and short runs
you may get away without termination resistors to Vtt. With these
resistors in place I found SSTL2_I adequate to drive without causing
overshoot. This takes much less power than SSTL2_II_DCI for the
externally terminated case.

> cu,
> Sean

Gabor wrote:
>>Third, remember that DDR-SDRAM has a MINIMAL clock rate
> This is less likely to bite you if you bothered to use DDR in the first
> place. Minimum for some chips is 83 MHz, others 66 MHz for DDR 1.
Well, I once used a Graphics-RAM (because of the 32bit-data-width,
wasn't a speed-critical application) and hooked it up to the plb_ddr.
Turns out the RAM had a minimal clock rate of 100MHz, which is equal to
the maximum clock rate the PLB can handle (or at least could handle back
then). Initially, I hadn't planned on running it at that speed, so of
course it didn't work until I went up to 100MHz. Took me awhile to
figure this out, though. Too many damn datasheets to read.

cu,
Sean

Thanks all for the infos !