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Old 04-30-2006, 09:01 PM
Posts: n/a
Default OPB Clocking Question

I am working with an embedded MicroBlaze project that has multiple
Xilinx cores and multiple custom IP cores. The FPGA hardware is used
to interface to our comapanie's "parts". Some of the custom core
functionality includes serial communications interfaces and special
time-critical data interfaces. We have two "flavors" of parts that the
FPGA hardware has to support. Each part outputs a reference clock that
we want to use inside the FPGA. However, each part outputs a different
clock frequency. I am working on reconciling the FPGA hardware in
order to run both parts with the same FPGA build.

The clock from the part is used to clock our custom IP modules. The
timing of the modules is derived from those clocks and works out
nicely. However, one of the part's clocks needs to be used at 1X
fequency, the other at 2X.

My first thought is to use the input clock from the part, which would
be one of two different values, and route that to a DCM. Then I would
use the 1X and the 2X output of that DCM. Both outputs would be fed to
an OPB software controlled mux. I forgot to mention that we also have
an on-board xtal that is currently used for ALL the clocking needs of
the FPGA. We run it at one of the part's frequencies so it is fine.
But a new part, with a new clock, is coming out that we have to
support. So the one clock solution will not work for both. I am

Anyways, I am thinking of using the xtal to feed a DCM that will derive
a clock that will drive the MicroBlaze, the Xilinx OPB cores, and the
above-mentioned clock switching mux. My concern is with driving the
OPB clock inputs on different cores with two different clocks.

Out cores would be driven by one of the two clocks selected from the
mux. The xilinx OPB cores would be driven by the xtal DCM clock. Is
it OK to do this? Do I have to consider clock domain issues when doing


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  #2 (permalink)  
Old 05-03-2006, 10:33 AM
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Default Re: OPB Clocking Question

Dear motty,

OPB peripherals MUST use the same (syncronous) clock, which should
probably not exceed 100 MHz. I suggest you do the conversion of data
from clk2x to clk (or from clk to clk2x) by adding a data mux. In this
way you get 32 bit data (OPB standard) from 16 bit data. If you want to
use a high-speed burst transfer (32bytes transfer/OPB_cycle) adding a
asyncronous fifo is almost inevitable.



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