Well, thanks for all your suggestions. As far as BRAMs, I would

rather use them elsewhere. I ended up with this rather verbose

code shown below. And I don't know how well it synthesizes, probably not

to well, because I think it is using several hundred LUTs. It's actually

a 62 ones counter and the bits can be turned off from the center out

with the B signals.

Brad

signal B00 : std_logic;

signal B01 : std_logic;

signal B02 : std_logic;

signal B03 : std_logic;

signal B04 : std_logic;

signal B05 : std_logic;

signal B06 : std_logic;

signal B07 : std_logic;

signal B08 : std_logic;

signal B09 : std_logic;

signal B10 : std_logic;

signal B11 : std_logic;

signal B12 : std_logic;

signal B13 : std_logic;

signal B14 : std_logic;

signal B15 : std_logic; -- center

signal B16 : std_logic;

signal B17 : std_logic;

signal B18 : std_logic;

signal B19 : std_logic;

signal B20 : std_logic;

signal B21 : std_logic;

signal B22 : std_logic;

signal B23 : std_logic;

signal B24 : std_logic;

signal B25 : std_logic;

signal B26 : std_logic;

signal B27 : std_logic;

signal B28 : std_logic;

signal B29 : std_logic;

signal B30 : std_logic;

signal EL00 : std_logic;

signal EL01 : std_logic;

signal EL02 : std_logic;

signal EL03 : std_logic;

signal EL04 : std_logic;

signal EL05 : std_logic;

signal EL06 : std_logic;

signal EL07 : std_logic;

signal EL08 : std_logic;

signal EL09 : std_logic;

signal EL10 : std_logic;

signal EL11 : std_logic;

signal EL12 : std_logic;

signal EL13 : std_logic;

signal EL14 : std_logic;

signal EL15 : std_logic;

signal EL16 : std_logic;

signal EL17 : std_logic;

signal EL18 : std_logic;

signal EL19 : std_logic;

signal EL20 : std_logic;

signal EL21 : std_logic;

signal EL22 : std_logic;

signal EL23 : std_logic;

signal EL24 : std_logic;

signal EL25 : std_logic;

signal EL26 : std_logic;

signal EL27 : std_logic;

signal EL28 : std_logic;

signal EL29 : std_logic;

signal EL30 : std_logic;

signal ER00 : std_logic;

signal ER01 : std_logic;

signal ER02 : std_logic;

signal ER03 : std_logic;

signal ER04 : std_logic;

signal ER05 : std_logic;

signal ER06 : std_logic;

signal ER07 : std_logic;

signal ER08 : std_logic;

signal ER09 : std_logic;

signal ER10 : std_logic;

signal ER11 : std_logic;

signal ER12 : std_logic;

signal ER13 : std_logic;

signal ER14 : std_logic;

signal ER15 : std_logic;

signal ER16 : std_logic;

signal ER17 : std_logic;

signal ER18 : std_logic;

signal ER19 : std_logic;

signal ER20 : std_logic;

signal ER21 : std_logic;

signal ER22 : std_logic;

signal ER23 : std_logic;

signal ER24 : std_logic;

signal ER25 : std_logic;

signal ER26 : std_logic;

signal ER27 : std_logic;

signal ER28 : std_logic;

signal ER29 : std_logic;

signal ER30 : std_logic;

signal sum_2_00 : std_logic_vector(1 downto 0);

signal sum_2_01 : std_logic_vector(1 downto 0);

signal sum_2_02 : std_logic_vector(1 downto 0);

signal sum_2_03 : std_logic_vector(1 downto 0);

signal sum_2_04 : std_logic_vector(1 downto 0);

signal sum_2_05 : std_logic_vector(1 downto 0);

signal sum_2_06 : std_logic_vector(1 downto 0);

signal sum_2_07 : std_logic_vector(1 downto 0);

signal sum_2_08 : std_logic_vector(1 downto 0);

signal sum_2_09 : std_logic_vector(1 downto 0);

signal sum_2_10 : std_logic_vector(1 downto 0);

signal sum_2_11 : std_logic_vector(1 downto 0);

signal sum_2_12 : std_logic_vector(1 downto 0);

signal sum_2_13 : std_logic_vector(1 downto 0);

signal sum_2_14 : std_logic_vector(1 downto 0);

signal sum_2_15 : std_logic_vector(1 downto 0);

signal sum_2_16 : std_logic_vector(1 downto 0);

signal sum_2_17 : std_logic_vector(1 downto 0);

signal sum_2_18 : std_logic_vector(1 downto 0);

signal sum_2_19 : std_logic_vector(1 downto 0);

signal sum_2_20 : std_logic_vector(1 downto 0);

signal sum_2_21 : std_logic_vector(1 downto 0);

signal sum_2_22 : std_logic_vector(1 downto 0);

signal sum_2_23 : std_logic_vector(1 downto 0);

signal sum_2_24 : std_logic_vector(1 downto 0);

signal sum_2_25 : std_logic_vector(1 downto 0);

signal sum_2_26 : std_logic_vector(1 downto 0);

signal sum_2_27 : std_logic_vector(1 downto 0);

signal sum_2_28 : std_logic_vector(1 downto 0);

signal sum_2_29 : std_logic_vector(1 downto 0);

signal sum_2_30 : std_logic_vector(1 downto 0);

signal sum_3_0 : std_logic_vector(2 downto 0);

signal sum_3_1 : std_logic_vector(2 downto 0);

signal sum_3_2 : std_logic_vector(2 downto 0);

signal sum_3_3 : std_logic_vector(2 downto 0);

signal sum_3_4 : std_logic_vector(2 downto 0);

signal sum_3_5 : std_logic_vector(2 downto 0);

signal sum_3_6 : std_logic_vector(2 downto 0);

signal sum_3_7 : std_logic_vector(2 downto 0);

signal sum_3_8 : std_logic_vector(2 downto 0);

signal sum_3_9 : std_logic_vector(2 downto 0);

signal sum_3_10 : std_logic_vector(2 downto 0);

signal sum_3_11 : std_logic_vector(2 downto 0);

signal sum_3_12 : std_logic_vector(2 downto 0);

signal sum_3_13 : std_logic_vector(2 downto 0);

signal sum_3_14 : std_logic_vector(2 downto 0);

signal sum_3_15 : std_logic_vector(2 downto 0);

signal sum_4_0 : std_logic_vector(3 downto 0);

signal sum_4_1 : std_logic_vector(3 downto 0);

signal sum_4_2 : std_logic_vector(3 downto 0);

signal sum_4_3 : std_logic_vector(3 downto 0);

signal sum_4_4 : std_logic_vector(3 downto 0);

signal sum_4_5 : std_logic_vector(3 downto 0);

signal sum_4_6 : std_logic_vector(3 downto 0);

signal sum_4_7 : std_logic_vector(3 downto 0);

signal sum_5_0 : std_logic_vector(4 downto 0);

signal sum_5_1 : std_logic_vector(4 downto 0);

signal sum_5_2 : std_logic_vector(4 downto 0);

signal sum_5_3 : std_logic_vector(4 downto 0);

signal sum_6_0 : std_logic_vector(5 downto 0);

signal sum_6_1 : std_logic_vector(5 downto 0);

signal sum_7_0 : std_logic_vector(6 downto 0);

begin

s15

rocess(clk)

begin

if(clk'event and clk='1') then

sum_2_15 <= "00";

if( B15='1') then

if( EL15='1' and ER15='1') then

sum_2_15 <= "10";

elsif( EL15='1' or ER15='1') then

sum_2_15 <= "01";

end if;

end if;

end if;

end process;

s1416

rocess(clk)

begin

if(clk'event and clk='1') then

sum_2_14 <= "00";

sum_2_16 <= "00";

if( B15='1' and B14='1' and B16='1' ) then

if( EL14='1' and ER14='1') then

sum_2_14 <= "10";

elsif( EL14='1' or ER14='1') then

sum_2_14 <= "01";

end if;

if( EL16='1' and ER16='1') then

sum_2_16 <= "10";

elsif( EL16='1' or ER16='1') then

sum_2_16 <= "01";

end if;

end if;

end if;

end process;

s1317

rocess(clk)

begin

if(clk'event and clk='1') then

sum_2_13 <= "00";

sum_2_17 <= "00";

if( B15='1' and B16='1' and B17='1'

and B14='1' and B13='1') then

if( EL13='1' and ER13='1') then

sum_2_13 <= "10";

elsif( EL13='1' or ER13='1') then

sum_2_13 <= "01";

end if;

if( EL17='1' and ER17='1') then

sum_2_17 <= "10";

elsif( EL17='1' or ER17='1') then

sum_2_17 <= "01";

end if;

end if;

end if;

end process;

s1218

rocess(clk)

begin

if(clk'event and clk='1') then

sum_2_12 <= "00";

sum_2_18 <= "00";

if( B15='1' and B16='1' and B17='1' and B18='1'

and B14='1' and B13='1' and B12='1' ) then

if( EL12='1' and ER12='1') then

sum_2_12 <= "10";

elsif( EL12='1' or ER12='1') then

sum_2_12 <= "01";

end if;

if( EL18='1' and ER18='1') then

sum_2_18 <= "10";

elsif( EL18='1' or ER18='1') then

sum_2_18 <= "01";

end if;

end if;

end if;

end process;

s1119

rocess(clk)

begin

if(clk'event and clk='1') then

sum_2_11 <= "00";

sum_2_19 <= "00";

if( B15='1' and B16='1' and B17='1' and B18='1' and B19='1'

and B14='1' and B13='1' and B12='1' and B11='1') then

if( EL11='1' and ER11='1') then

sum_2_11 <= "10";

elsif( EL11='1' or ER11='1') then

sum_2_11 <= "01";

end if;

if( EL19='1' and ER19='1') then

sum_2_19 <= "10";

elsif( EL19='1' or ER19='1') then

sum_2_19 <= "01";

end if;

end if;

end if;

end process;

s1020

rocess(clk)

begin

if(clk'event and clk='1') then

sum_2_10 <= "00";

sum_2_20 <= "00";

if( B15='1' and B16='1' and B17='1' and B18='1' and B19='1'

and B20='1'

and B14='1' and B13='1' and B12='1' and B11='1'

and B10='1') then

if( EL10='1' and ER10='1') then

sum_2_10 <= "10";

elsif( EL10='1' or ER10='1') then

sum_2_10 <= "01";

end if;

if( EL20='1' and ER20='1') then

sum_2_20 <= "10";

elsif( EL20='1' or ER20='1') then

sum_2_20 <= "01";

end if;

end if;

end if;

end process;

s0921

rocess(clk)

begin

if(clk'event and clk='1') then

sum_2_09 <= "00";

sum_2_21 <= "00";

if( B15='1' and B16='1' and B17='1' and B18='1' and B19='1'

and B20='1' and B21='1'

and B14='1' and B13='1' and B12='1' and B11='1'

and B10='1' and B09='1'

) then

if( EL09='1' and ER09='1') then

sum_2_09 <= "10";

elsif( EL09='1' or ER09='1') then

sum_2_09 <= "01";

end if;

if( EL21='1' and ER21='1') then

sum_2_21 <= "10";

elsif( EL21='1' or ER21='1') then

sum_2_21 <= "01";

end if;

end if;

end if;

end process;

s0822

rocess(clk)

begin

if(clk'event and clk='1') then

sum_2_08 <= "00";

sum_2_22 <= "00";

if( B15='1' and B16='1' and B17='1' and B18='1' and B19='1'

and B20='1' and B21='1' and B22='1'

and B14='1' and B13='1' and B12='1' and B11='1'

and B10='1' and B09='1' and B08='1'

) then

if( EL08='1' and ER08='1') then

sum_2_08 <= "10";

elsif( EL08='1' or ER08='1') then

sum_2_08 <= "01";

end if;

if( EL22='1' and ER22='1') then

sum_2_22 <= "10";

elsif( EL22='1' or ER22='1') then

sum_2_22 <= "01";

end if;

end if;

end if;

end process;

s0723

rocess(clk)

begin

if(clk'event and clk='1') then

sum_2_07 <= "00";

sum_2_23 <= "00";

if( B15='1' and B16='1' and B17='1' and B18='1' and B19='1'

and B20='1' and B21='1' and B22='1' and B23='1'

and B14='1' and B13='1' and B12='1' and B11='1'

and B10='1' and B09='1' and B08='1' and B07='1'

) then

if( EL07='1' and ER07='1') then

sum_2_07 <= "10";

elsif( EL07='1' or ER07='1') then

sum_2_07 <= "01";

end if;

if( EL23='1' and ER23='1') then

sum_2_23 <= "10";

elsif( EL23='1' or ER23='1') then

sum_2_23 <= "01";

end if;

end if;

end if;

end process;

s0624

rocess(clk)

begin

if(clk'event and clk='1') then

sum_2_06 <= "00";

sum_2_24 <= "00";

if( B15='1' and B16='1' and B17='1' and B18='1' and B19='1'

and B20='1' and B21='1' and B22='1' and B23='1'

and B24='1'

and B14='1' and B13='1' and B12='1' and B11='1'

and B10='1' and B09='1' and B08='1' and B07='1'

and B06='1'

) then

if( EL06='1' and ER06='1') then

sum_2_06 <= "10";

elsif( EL06='1' or ER06='1') then

sum_2_06 <= "01";

end if;

if( EL24='1' and ER24='1') then

sum_2_24 <= "10";

elsif( EL24='1' or ER24='1') then

sum_2_24 <= "01";

end if;

end if;

end if;

end process;

s0525

rocess(clk)

begin

if(clk'event and clk='1') then

sum_2_05 <= "00";

sum_2_25 <= "00";

if( B15='1' and B16='1' and B17='1' and B18='1' and B19='1'

and B20='1' and B21='1' and B22='1' and B23='1'

and B24='1' and B25='1'

and B14='1' and B13='1' and B12='1' and B11='1'

and B10='1' and B09='1' and B08='1' and B07='1'

and B06='1' and B05='1'

) then

if( EL05='1' and ER05='1') then

sum_2_05 <= "10";

elsif( EL05='1' or ER05='1') then

sum_2_05 <= "01";

end if;

if( EL25='1' and ER25='1') then

sum_2_25 <= "10";

elsif( EL25='1' or ER25='1') then

sum_2_25 <= "01";

end if;

end if;

end if;

end process;

s0426

rocess(clk)

begin

if(clk'event and clk='1') then

sum_2_04 <= "00";

sum_2_26 <= "00";

if( B15='1' and B16='1' and B17='1' and B18='1' and B19='1'

and B20='1' and B21='1' and B22='1' and B23='1'

and B24='1' and B25='1' and B26='1'

and B14='1' and B13='1' and B12='1' and B11='1'

and B10='1' and B09='1' and B08='1' and B07='1'

and B06='1' and B05='1' and B04='1'

) then

if( EL04='1' and ER04='1') then

sum_2_04 <= "10";

elsif( EL04='1' or ER04='1') then

sum_2_04 <= "01";

end if;

if( EL26='1' and ER26='1') then

sum_2_26 <= "10";

elsif( EL26='1' or ER26='1') then

sum_2_26 <= "01";

end if;

end if;

end if;

end process;

s0327

rocess(clk)

begin

if(clk'event and clk='1') then

sum_2_03 <= "00";

sum_2_27 <= "00";

if( B15='1' and B16='1' and B17='1' and B18='1' and B19='1'

and B20='1' and B21='1' and B22='1' and B23='1'

and B24='1' and B25='1' and B26='1' and B27='1'

and B14='1' and B13='1' and B12='1' and B11='1'

and B10='1' and B09='1' and B08='1' and B07='1'

and B06='1' and B05='1' and B04='1' and B03='1'

) then

if( EL03='1' and ER03='1') then

sum_2_03 <= "10";

elsif( EL03='1' or ER03='1') then

sum_2_03 <= "01";

end if;

if( EL27='1' and ER27='1') then

sum_2_27 <= "10";

elsif( EL27='1' or ER27='1') then

sum_2_27 <= "01";

end if;

end if;

end if;

end process;

s0228

rocess(clk)

begin

if(clk'event and clk='1') then

sum_2_02 <= "00";

sum_2_28 <= "00";

if( B15='1' and B16='1' and B17='1' and B18='1' and B19='1'

and B20='1' and B21='1' and B22='1' and B23='1'

and B24='1' and B25='1' and B26='1' and B27='1'

and B28='1'

and B14='1' and B13='1' and B12='1' and B11='1'

and B10='1' and B09='1' and B08='1' and B07='1'

and B06='1' and B05='1' and B04='1' and B03='1'

and B02='1'

) then

if( EL02='1' and ER02='1') then

sum_2_02 <= "10";

elsif( EL02='1' or ER02='1') then

sum_2_02 <= "01";

end if;

if( EL28='1' and ER28='1') then

sum_2_28 <= "10";

elsif( EL28='1' or ER28='1') then

sum_2_28 <= "01";

end if;

end if;

end if;

end process;

s0129

rocess(clk)

begin

if(clk'event and clk='1') then

sum_2_01 <= "00";

sum_2_29 <= "00";

if( B15='1' and B16='1' and B17='1' and B18='1' and B19='1'

and B20='1' and B21='1' and B22='1' and B23='1'

and B24='1' and B25='1' and B26='1' and B27='1'

and B28='1' and B29='1'

and B14='1' and B13='1' and B12='1' and B11='1'

and B10='1' and B09='1' and B08='1' and B07='1'

and B06='1' and B05='1' and B04='1' and B03='1'

and B02='1' and B01='1'

) then

if( EL01='1' and ER01='1') then

sum_2_01 <= "10";

elsif( EL01='1' or ER01='1') then

sum_2_01 <= "01";

end if;

if( EL29='1' and ER29='1') then

sum_2_29 <= "10";

elsif( EL29='1' or ER29='1') then

sum_2_29 <= "01";

end if;

end if;

end if;

end process;

s0030

rocess(clk)

begin

if(clk'event and clk='1') then

sum_2_00 <= "00";

sum_2_30 <= "00";

if( B15='1' and B16='1' and B17='1' and B18='1' and B19='1'

and B20='1' and B21='1' and B22='1' and B23='1'

and B24='1' and B25='1' and B26='1' and B27='1'

and B28='1' and B29='1' and B30='1'

and B14='1' and B13='1' and B12='1' and B11='1'

and B10='1' and B09='1' and B08='1' and B07='1'

and B06='1' and B05='1' and B04='1' and B03='1'

and B02='1' and B01='1' and B00='1'

) then

if( EL00='1' and ER00='1') then

sum_2_00 <= "10";

elsif( EL00='1' or ER00='1') then

sum_2_00 <= "01";

end if;

if( EL30='1' and ER30='1') then

sum_2_30 <= "10";

elsif( EL30='1' or ER30='1') then

sum_2_30 <= "01";

end if;

end if;

end if;

end process;

-- I numberered the partial sums from the center out

-- in case there may be some future additional logic

-- that could share these partial sums.

s3

rocess(clk)

begin

if(clk'event and clk='1') then

sum_3_0 <= '0'&sum_2_15;

sum_3_1 <= ('0'&sum_2_14) + ('0'&sum_2_16);

sum_3_2 <= ('0'&sum_2_13) + ('0'&sum_2_17);

sum_3_3 <= ('0'&sum_2_12) + ('0'&sum_2_18);

sum_3_4 <= ('0'&sum_2_11) + ('0'&sum_2_19);

sum_3_5 <= ('0'&sum_2_10) + ('0'&sum_2_20);

sum_3_6 <= ('0'&sum_2_09) + ('0'&sum_2_21);

sum_3_7 <= ('0'&sum_2_08) + ('0'&sum_2_22);

sum_3_8 <= ('0'&sum_2_07) + ('0'&sum_2_23);

sum_3_9 <= ('0'&sum_2_06) + ('0'&sum_2_24);

sum_3_10 <= ('0'&sum_2_05) + ('0'&sum_2_25);

sum_3_11 <= ('0'&sum_2_04) + ('0'&sum_2_26);

sum_3_12 <= ('0'&sum_2_03) + ('0'&sum_2_27);

sum_3_13 <= ('0'&sum_2_02) + ('0'&sum_2_28);

sum_3_14 <= ('0'&sum_2_01) + ('0'&sum_2_29);

sum_3_15 <= ('0'&sum_2_00) + ('0'&sum_2_30);

end if;

end process;

s4

rocess(clk)

begin

if(clk'event and clk='1') then

sum_4_0 <= ('0'&sum_3_0) + ('0'&sum_3_1);

sum_4_1 <= ('0'&sum_3_2) + ('0'&sum_3_3);

sum_4_2 <= ('0'&sum_3_4) + ('0'&sum_3_5);

sum_4_3 <= ('0'&sum_3_6) + ('0'&sum_3_7);

sum_4_4 <= ('0'&sum_3_8) + ('0'&sum_3_9);

sum_4_5 <= ('0'&sum_3_10) + ('0'&sum_3_11);

sum_4_6 <= ('0'&sum_3_12) + ('0'&sum_3_13);

sum_4_7 <= ('0'&sum_3_14) + ('0'&sum_3_15);

end if;

end process;

s5

rocess(clk)

begin

if(clk'event and clk='1') then

sum_5_0 <= ('0'&sum_4_0) + ('0'&sum_4_1);

sum_5_1 <= ('0'&sum_4_2) + ('0'&sum_4_3);

sum_5_2 <= ('0'&sum_4_4) + ('0'&sum_4_5);

sum_5_3 <= ('0'&sum_4_6) + ('0'&sum_4_7);

end if;

end process;

s6

rocess(clk)

begin

if(clk'event and clk='1') then

sum_6_0 <= ('0'&sum_5_0) + ('0'&sum_5_1);

sum_6_1 <= ('0'&sum_5_2) + ('0'&sum_5_3);

end if;

end process;

s7

rocess(clk)

begin

if(clk'event and clk='1') then

sum_7_0 <= ('0'&sum_6_0) + ('0'&sum_6_1);

end if;

end process;