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Old 07-12-2005, 09:48 PM
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Default Observations on passing clock constraints through DCM in Synplify 8.1

Hello All,

Please have a look at my observations below and let me know,whether you
agree with them.Or, if you would like to add your expert comments based
on your experiences,please do.

I am using Synplify 8.1 for synthesizing my design(which uses multiple
DCMs) for a Xilinx Virtex-4 device.

WITHOUT CONSTRAINTS: the tool infers clk0 ,clk2x and clkfx clock
outputs from the DCM, if you don't specify any constraints to the tool
apart from the auto constraints(default 1 MHZ).As expected,it does not
propagate the DCM input clock constraints and doesn't understand the 2x
and fx(M/D values ).

WITH CONSTRAINTS: when you specify constraints to the input
clock(clkin) of the DCM then it happily stops inferring clk0 but it
does infer clk2x and clkfx DCM outputs . The tool doesn't constrain the
clkfx and clk2x output clocks according to the values set in the dcm
but instead it just constrains it to the default (1 Mhz).

WITH XC_PROPS : I went through the Synplify reference manuals ,where it
was instructed to use xc_props to specify the
clkfx_multiply,clkfx_divide etc attributes (In case, the propagation of
the constraints don't work properly). Next ,I tried with these
attributes attached to the DCM instances in SDC as well as the code.But
it could not drive synplify to do the automatic clkfx and clk2x
constraint calculation.

At last , I had to find the clkfx and clk2x net names from the log file
(.srr) and apply the constraints to them. Thankfully , this worked!!!

Please, tell me if this issue is something which has been an accepted
fact with Synplify synthesis or is there some other way out of this ?


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