FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal


Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 01-15-2005, 07:58 PM
Posts: n/a
Default No device found in Boundary Scan Chain, for Xilinx PC4 Cable

Hi All,

I am learning how to program Xilinx CPLD, starting with XPLA3
(XCR3032XL)and Parallel Cable IV. I consistently encounted the problem
from iMPACT - "No device detected in Boundary Scan Chain" when I tried
to initialize the Boundary Scan Chain. The error no. is 585 and I am in
JTAG mode. I am not using developing board since I'd like to build an
embedded system afterwards.

I followed the hint given by ISE6.3i for checking - The pin layout, The
connection, The Power level. But no problem found there.

..I have read from this group saying Port-En pin should be put high when
init, I tried this but failed. I put Port-En back to low.

..I am using battery cells and resister network as the power supply for
the XCR3032XL. The Voltage is 3.3-3.6V and the Current is 1.8mA.

..I am using PS2 mouse port as the power supply for the PC4 Cable. The
voltage is 5.04V and the Current is changing around 10mA, far lower
than the recommended but this is one of the standard config for PC4

..The cable is connected and Parallel port is in ECP mode.

..I have added the .jed file into iMPACT before initializing the cable.
And I get the same problem.

..As I debugged the chain, I found the TDO sticked to be "1" whatever
the TDI was.

So what's the issue? Is it to say PC4 doesn't support XCR3032XL?
Appreciation for any idea!


Reply With Quote


Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On

Similar Threads
Thread Thread Starter Forum Replies Last Post
Xilinx JTAG Parallel IV cable and INITIALIZING CHAIN Ronald Chung FPGA 6 02-14-2010 05:30 PM
JTAG scan chain [email protected] Verilog 0 01-11-2007 12:54 AM
GPIO,SCAN CHAIN and BIST rsk Verilog 1 02-24-2005 09:29 PM
JTAG boundary scan xc2v6000 T. Irmen FPGA 1 11-16-2004 12:07 PM

All times are GMT +1. The time now is 05:23 PM.

Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved