FPGA Central

I've just moved from Quartus 4.0 to 5.0, re-generated a Nios design
under SoPC Builder, and run the design through Quartus.

The timing has gone from almost 90Mhz before to 72Mhz now.

Anyone experienced similar speed-downs?

Alan

Hi Alan,

> I've just moved from Quartus 4.0 to 5.0, re-generated a Nios design
> under SoPC Builder, and run the design through Quartus.
> The timing has gone from almost 90Mhz before to 72Mhz now.
> Anyone experienced similar speed-downs?

By any chance, did you set an aggressive timing constraint? If not, then
Quartus (as of some version between 4.0 and 4.2 -- I forget which) will
automatically stop working hard on timing once it sees that your design (a)
meets timing and (b) will likely be able to route. This saves you compile
time, but also means that push-button compilation without a tight constraint
may show a slowdown.

If this is not the issue, please provide some more information, such as what
Nios options you selected and what device you are targeting.

Thanks,

Paul Leventis
Altera Corp.

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