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Old 03-22-2005, 03:24 PM
Alessandro Strazzero
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Default NIOS II power-on reset

Dear everybody,

I have a problem on some production boards based on the Altera Cyclone FPGA.
The boards have installed NIOS II CPU. The problem regards the power-on
sequence because some boards are not able to power-up correctly (seems NIOS II
CPU doesn't execute first operative code).

The development was made on a C7 speed grade FPGA and I didn't experience such
problem. The boards where the problems were detected have installed the C8
speed grade Cyclone.

The power-on and reset circuitry comes from Altera's Cyclone development board.
I think the problem is around the FPGA speed grade, but I was not able to find
the reason. My system works at 64 MHz which is a well supported frequency by
the C8 speed grade device.

Did you experience my same problem ? Any tips to workaround the problem will
be appreciated

Best Regards

/Alessandro
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  #2 (permalink)  
Old 03-22-2005, 05:18 PM
Dan NITA
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Default Re: NIOS II power-on reset

Hi,



Maybe a excessive power-on current?



Dan.




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  #3 (permalink)  
Old 03-24-2005, 07:59 AM
Jon Keeble
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Posts: n/a
Default Re: NIOS II power-on reset

Checkout the voltage waveform as power is applied.
You may find that a current surge (in the fpga) that takes place as the
voltage ramps up makes this non-monotonic.
This may upset various components on the board, if not the fpga itself.

Regards

Jon


"Alessandro Strazzero" <[email protected]> wrote in message
news:[email protected] om...
> Dear everybody,
>
> I have a problem on some production boards based on the Altera Cyclone

FPGA.
> The boards have installed NIOS II CPU. The problem regards the power-on
> sequence because some boards are not able to power-up correctly (seems

NIOS II
> CPU doesn't execute first operative code).
>
> The development was made on a C7 speed grade FPGA and I didn't experience

such
> problem. The boards where the problems were detected have installed the C8
> speed grade Cyclone.
>
> The power-on and reset circuitry comes from Altera's Cyclone development

board.
> I think the problem is around the FPGA speed grade, but I was not able to

find
> the reason. My system works at 64 MHz which is a well supported frequency

by
> the C8 speed grade device.
>
> Did you experience my same problem ? Any tips to workaround the problem

will
> be appreciated
>
> Best Regards
>
> /Alessandro



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